Title: ECSI Workshop on TLM Users Experience
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Accellera invites you to attend these free events at the DATE Conference 2007, Nice, France:
Accellera Low-Power Workshop Register for this Workshop
Tuesday, April 17, 2007
12:00-15:00 CET
Novotel, Matisse/Chagall Conference Room
How will you define, verify and implement your next low power design? Join Mentor Graphics, Synopsys and Magma for an educational lunch seminar on Accellera's Unified Low Power Format (UPF) standard. See how UPF extends logic design specifications with low power information such as isolation and retention strategies, power domain definition, supply distribution and switching for verification and implementation.
Accellera/IEEE Joint Meeting and VHDL 3.0 Tutorial Register for this Meeting
Tuesday, April 17, 2007
15:00 -18:00 CET
Acropolis, Gallieni 4
This meeting includes a tutorial about the VHDL 3.0 Standard, presented by Jim Lewis of SynthWorks, with an overview of the changes to the standard, a detailed tutorial on the fixed and floating point packages, and a look into the next set of revisions currently being worked on in committee.
Description of the tutorial: In July 2006, the Accellera board approved a revision VHDL standard (revision 3.0) put forward by the Accellera VHDL Technical Subcommittee (VHDL TSC). As an Accellera standard, revision 3.0 is ready for industry adoption.
This standard was a tag-team effort between the IEEE and Accellera committees. Work on this standard started as the IEEE VHDL Analysis and Standardization Group's (VASG) VHDL-200X effort in early 2003. The VHDL-200X team made great technical progress, however, it failed to find a funding model to fund the LRM editing.
In June 2005, the VASG transitioned the work to the Accellera VHDL TSC. The Accellera VHDL TSC merged the VHDL-200X proposals with additional items submitted by Accellera VHDL TSC members. It then prioritized the proposals based on user input ensuring that proposals selected for the standard are what the user community wants. It then did super-human work to finalize the standard and funded the LRM editing.
An abbreviated list of changes includes:
- PSL directly in VHDL code
- IP protection mechanisms
- Packages with generics.
- Formal Generic Types and Subprograms
- Fixed and floating point packages.
- Composite types (records and arrays) that permit elements to be unconstrained arrays (facilitates creation of matrix types)
Hierarchical signal reference.
- Simplified sensitivity lists using process(all)
- Simplified conditionals (if, ...)
- Simplified case statements
This tutorial includes an overview of the changes to the standard, a detailed tutorial on the fixed and floating point packages, and a look into the next set of revisions currently being worked on in committee.
Hope to see you there!
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