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CALL FOR PARTICIPATION & SUBMISSION
Workshop on the High-Level Synthesis: "The New Wave of the High-Level Synthesis"
As part of the 2008 International Conference on Design, Automation & Test in Europe (DATE08)
Munich, Germany
March 14, 2008
(Submission Deadline: February 22, 2008)
Description:
The successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimised gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction. In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow - a VHDL/Verilog RTL specification,
followed by logical and physical synthesis - is indeed no more suitable. Thus, actual complex SoCs need new ESL level tools in order to raise the specification abstraction level up to the algorithmic / behavioural one. Languages like C/C++/SystemC offer high abstraction levels. However, in order to provide the designers with an efficient automated path to implementation, new high-level synthesis tools are required. Several commercial and academic tools are available today: Bluespec from
Bluespec, Catapult from Mentor Graphics, Cyber from NEC, Cynthesizer from Forte Design Systems, PICO from Synfora & GAUT from UBS University, SPARK from UCSD, UGH from TIMA/LIP6, xPilot from UCLA&
The main expectations from the system design teams
concern both methods and tools supporting better management of the design complexity and reduction of the design cycle all together, breaking the trend to compromise evaluation of various design implementation options. Designing at higher levels of abstraction is an obvious way as it allows a better coping with the system design complexity, to verify earlier in the design process and to increase code reuse.
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Target Audience:
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This workshop on High-Level Synthesis will provide an overview of existing and emerging solutions provided by both industrial partners (EDA companies) and research institutions in this domain. It will give an outline of HLS methods and tools available currently on the market and bring the details on their applicability, performance, and strengths. Finally, the event will create a discussion platform for experience exchange between providers of synthesis technology and industry users. |
Paper Submissions:
Submissions are invited in the form of 1-page extended abstract describing the novelties and advantages of the work.
Submissions must be sent before February, 22th in as PDF file to < [EMAIL PROTECTED] > with "DATE'08 HLS workshop" as subject.
All submissions will be evaluated with regard to their suitability for the workshop, originality and technical soundness.
Selected submissions will be accepted for poster / interactive presentation.
If you have any questions about paper submission or the workshop, please contact [EMAIL PROTECTED]. |
Agenda:
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0830 - 0840 |
Introduction
P Coussy, University of South Brittany , FR and A Morawiec, ECSI, FR |
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Session 1: EDA tool presentations |
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0845 - 0900 |
Catapult Synthesis: a Proven Approach for the Creation of Complex Hardware Designs
T Bollart, Mentor Graphics FR |
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0905 - 0920
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Enabling DSP System Designs with High Level Design Methodologies & Tools
J Heighton, Xilinx, IR |
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0925 - 0940 |
Cynthesizer: the Forte SystemC synthesis tool
M Meredith, Forte Design Systems, US |
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0945 - 1000
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New Opportunities for High-Level Synthesis
J Cong, UCLA/AutoESL, US |
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1000 - 1015 |
BREAK |
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Session 2: Research directions |
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1020 - 1040 |
HLS and Cost of Design
R Gupta, UCSD , US |
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1045 - 1105
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Multi-Mode Architecture Design with High-Level Synthesis
P Coussy, University of South Brittany , FR |
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1110 - 1130
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Ant Colony Optimization for High Level Synthesis
R Kastner, UCSB , US |
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1135 - 1155 |
User Guided High level synthesis
F Pétrot, TIMA Laboratory, FR |
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1200 - 1300 |
LUNCH |
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1300 - 1430 |
Session 3: Poster / Demonstration / Interactive presentation
Program to be defined You are invited to participate and submit your contributions to the DATE08 workshop on High-Level Synthesis.
Submissions are invited in the form of 1-page extended abstract describing the novelties and advantages of the work.
Submissions must be sent before February, 22th in as PDF file to < [EMAIL PROTECTED] > with "DATE'08 HLS workshop" as subject.
All submissions will be evaluated with regard to their suitability for the workshop, originality and technical soundness.
Selected submissions will be accepted for poster / interactive presentation. |
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1430 - 1445 |
BREAK |
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1445 - 1645 |
Session 4 : The Future of High-Level Synthesis
The Limits of Current HLS Offer : What is Needed for a Wider Adoption
P Urard, STMicroelectronics, FR
How to Make Algorithmic Synthesis as Ubiquitous as Logic Synthesis
V Katail, Synfora , US
"All-in-C" SoC Synthesis and Verification with CyberWorkBench
K Wakabayashi, NEC, JP
Industrial Usage of High-Level Synthesis
W Ecker, Infineon , DE
Synthesis Semantics for SystemC
A Takach, Chair of the OSCI Synthesis Working Group, US
Panel Discussion
With all session 4 presenters |
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1645 |
CLOSE |
Important Dates:
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Paper Submissions |
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February 22, 2008 |
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Acceptance Notification |
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February 29, 2008 |
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Poster and Registration Due |
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March 14, 2008 |
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