Call for Submissions and Participation

DATE 2008 Friday Workshop on
Impact of Process Variability on Design and Test

ICM, Munich, Germany, Friday, March 14, 2008.
http://www.date-conference.com/conference/2008/prog/progdetail.php?progid=W2

Abstract submission deadline: March 1, 2008.
Early registration deadline: February 20, 2008.


WORKSHOP DESCRIPTION
Integrated circuit technology continues to shrink. Mainstream
semiconductors are starting to be produced at the 45nm technology node,
where transistors and wires measure less than 100 atoms across. The
discrepancies between lithography wavelengths and circuit feature sizes
increase. Lower power supply levels and increasing operating speeds
significantly reduce noise margins and increase variations in process,
device and design parameters. Consequently, it is increasingly difficult
to control the fabrication process precisely enough to maintain
uniformity. The inherent randomness of materials used in fabrication at
nanoscopic scales means that performance will be increasingly variable,
not only from die-to-die but also within each individual die.

Process variation cannot be solved by improving manufacturing
tolerances. Variability must be reduced by new device technology or
managed by design in order for scaling to continue. Within-die
performance variation also imposes new challenges for test methods. Test
hardware must be embedded in the design to detect errors dynamically,
isolate and confine faults, reconfigure the system to work around faults
using spare hardware, and recover from errors on the fly. This will
become increasingly important as devices experience parametric
degradation over time, requiring run-time reconfiguration. This workshop
will provide a forum for researchers from industry and academia where
the latest results can be presented and ideas exchanged between those
working on different approaches to dealing with variability.

The scope of this workshop covers all aspects of process variation. At
the transistor level, this includes new devices to replace CMOS in order
to reduce variability, and the modelling of transistor devices at atomic
scales so variation can be understood. From the viewpoint of fabrication
technology, new techniques and CAD tools for predicting and compensating
for the effect of variability in processes are of interest. At the
circuit and system level, tools and design methods must be aware of
variation, without adding extra complexity that renders design
intractable. Process variation-aware test and reliability methods
together with various design techniques that allow circuits and systems
to adapt variability are also of particular relevance.

By bringing together researchers from different areas of expertise, this
workshop aims to encourage collaborative research that tackles the
problems of process variation from several levels simultaneously.


PROGRAM AND PARTICIPATION
The workshop includes seven very interesting invited talks - however a
significant part of the workshop will be based around poster
presentations, to maximise the opportunities for discussion and
interaction amongst all participants.

There will be two one-hour sessions during the workshop for poster
presentations. The format of the posters will be A0 portrait. A title
and a brief abstract of the poster should be sent to Gert Jervan
([EMAIL PROTECTED]), Mladen Berekovic ([EMAIL PROTECTED]) or
Pete Sedcole ([EMAIL PROTECTED]).

Participation requires registration and a registration fee. Discounted
registration is available through the DATE'08 web site only until
February 20, 2008. Full-fee registration will also be possible on-site
in Munich, Germany.

For more information see:
http://www.date-conference.com/conference/2008/prog/progdetail.php?progid=W2


Please feel free to forward this on to anyone who you believe may be
interested.


Gert Jervan ([EMAIL PROTECTED])
Mladen Berekovic ([EMAIL PROTECTED])
Pete Sedcole ([EMAIL PROTECTED])



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