{Spam?} DAC'08 Workshop > High-Level Synthesis: Back to the Future - June 8, 2008 - Call for Poster Submissions

[training]

Title: FRIDAY 20 APRIL, 2007

High-Level Synthesis: Back to the Future   DAC’08 Workshop   June 8, 2008 – 8:30-17:30 Anaheim Convention Center – Anaheim, CA, USA - Room 203b www.dac.com     Updated information: http://www.dac.com/events/eventdetails.aspx?id=77-155   Organised in conjunction with: MEMOCODE’08 - June 5-7, Anaheim - memocode-conference.com       Poster submission deadline: April 30, see session 3 for more information. Acceptation notification: May 5   Organisers: Philippe Coussy, University of South Brittany UBS, Lab-STICC., Lorient, FR (Chair) Adam Morawiec, ECSI, Grenoble, FR (Co-Chair)   Description: The successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction. In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow - a VHDL/Verilog RTL specification, followed by logical and physical synthesis - is indeed no more suitable. Thus, actual complex SoCs need new ESL level tools in order to raise the specification abstraction level up to the algorithmic / behavioral one. Languages like C/C++/SystemC offer high abstraction levels. However, in order to provide the designers with an efficient automated path to implementation, new high-level synthesis tools are required. Several commercial and academic tools are available today: Bluespec from Bluespec, Catapult from Mentor Graphics, Cyber from NEC, Cynthesizer from Forte Design Systems, PICO from Synfora … GAUT from UBS University, SPARK from UCSD, UGH from TIMA/LIP6, xPilot from UCLA…   The main expectations from the system design teams concern both methods and tools supporting better management of the design complexity and reduction of the design cycle all together, breaking the trend to compromise evaluation of various design implementation options. Designing at higher levels of abstraction is an obvious way as it allows a better coping with the system design complexity, to verify earlier in the design process and to increase code reuse.   Target Audience: This workshop on High-Level Synthesis will provide an overview of existing and emerging solutions provided by both industrial partners (EDA companies) and research institutions in this domain. It will give an outline of HLS methods and tools available currently on the market and bring the details on their applicability, performance, and strengths. Finally, the event will create a discussion platform for experience exchange between providers of synthesis technology and industry users.       0830 – 0840 Introduction Philippe Coussy, University of South Brittany, France & Adam Morawiec, ECSI, France   0840 - 1010   0840 – 0900     0900 – 0920     0920 – 0940     0940 – 1000   Session 1: Architecture and design flow I   The Real High-Level Synthesis Daniel D. Gajski, University of California at Irvine, USA   From executable specifications to high-quality implementations using Bluespec Rishiyur S. Nikhil, Bluespec, USA   Integrating Post-programmability into the High-Level Synthesis Equation Scott Mahlke, University of Michigan, USA   Synthesis and Optimization Foundation for ESL 2.0 Jason Cong,  AutoESL, USA   1010 – 1020 BREAK   1020 - 1200   1020 – 1040     1040 – 1100     1100 – 1120       1120 – 1150 Session 2: Low-power and Thermal Aware HLS   System-Level Power Management R. Gupta, University of California, San Diego, USA   High-level Synthesis: Optimizing for Low Power Design A. Takach , Mentor Graphics, USA   When High-Level Synthesis Meets Power, Thermal, and Reliability Challenges Li Shang, Colorado University, USA Robert P. Dick, Northwestern University – USA   Power Optimizing High Level Synthesis Eike Schmidt, ChipVision, Germany   1200 – 1330 Session 3: Posters / Demonstrations / Interactive presentations (with Lunch Buffet)   Program to be defined based on the proposal submissions   You are invited to participate and submit your contributions to the DAC’08 workshop on High-Level Synthesis. Full information available on the DAC’08 web site - www.dac.com   Submissions are invited in the form of 1-page extended abstract describing the novelties and advantages of the work. Submissions must be sent in as PDF file to < [EMAIL PROTECTED] > with “DAC’08 HLS workshop” as subject. All submissions will be evaluated with regard to their suitability for the workshop, originality and technical soundness. Selected submissions will be accepted for interactive presentation.   1330 – 1500   1330 – 1350     1350 – 1410     1410 – 1430     1430 – 1450 Session 4: Architecture and design flow II   HLS as an enabling technology: some complex examples Arvind, Massachusetts Institute of Technology, USA   Applying SystemC Synthesis to all your design challenges Michael Meredith, Forte Design Systems – USA   Latency Insensitive Scalable System Synthesis F. Brewer, University of California, Santa Barbara, USA   ESL: A Picture Paints A Thousand Words Chris Eddington, Synplicity Inc., USA   1500 – 1515 BREAK   1515 – 1625   1515 – 1535     1535 – 1555     1555 – 1610     1610 – 1625 Session 5: Design flow and User Needs   C-based SoC Design Flow with "CyberWorkBench" K. Wakabayashi, NEC, Japan   How to make algorithmic synthesis as ubiquitous as logic synthesis Vinod Kathail, Synfora, USA   HLS Evolution and Needs from an IDM Point of View Nitin Chawla, STMicroelectronics, India   HLS for SoC: How to Integrate New Class of Algorithms in Existing Platform Gael Clave, Texas Instruments, France   1625 – 1710 Panel with participants from User Companies, EDA and Academia     1710 – 1730 Wrap-up & Close     Registration: www.dac.com   More information: Philippe Coussy - [EMAIL PROTECTED]             Adam Morawiec – [EMAIL PROTECTED]

_________________________________________________________________________________
mozart-users mailing list                               
mozart-users@mozart-oz.org
http://www.mozart-oz.org/mailman/listinfo/mozart-users