Updated program at: http://www.dac.com/events/eventdetails.aspx?id=77-167 Sponsors: OCP-IP, ARM, DAFCA, GiDEL, Magillem, Synplicity Workshop Description: Debug is one of the
biggest factors in delaying shipment of a product. The problem is exacerbated
with the introduction of multicore technology.
SoC-level multicore debug is a topic that has
received considerable visibility, due to its importance in improving the
verification and analysis of SoCs and improving time to market of silicon
products. A fair amount of activity has gone into standardization of the
interfaces, features, and methodologies related to multicore
debug. There is also considerable discussions and development work going into
the standardization of the software interfaces used to debug multicore applications. This represents a challenge in
scaling software development tools such as debuggers and simulators to support
chips with 10s or 100s of cores. This workshop, based on the two successful
workshops organized by ECSI in 2007 and in early 2008, provides an overview
into several standards efforts related to multicore
debug with representation from IEEE working groups including Nexus Forum, IJTAG
(IEEE P1687), as well as working groups within the OCP-IP, Multicore
Association, SPIRIT, and Eclipse consortiums. In addition industrial project
SPRINT contribution to standardization will be presented. The workshop also
shows a vast set of requirements expressed by the system and SoC companies with
regard to debug methods and tools. Furthermore, the event will also present and
contrast existing commercial debug tools. Chairs: o
Dr o
Dr Preliminary Agenda: Session 1: Introduction to Challenges
in System and SoC Debug (9:00-9:30 [0h30]) This session will present
major problems in the area of debug of complex systems. An overview of emerging
solutions and a “topology map” of the existing standardization activities will
be presented, as well as their relations to industry initiatives and de facto
standards. Presenter: Session 2: Industry Requirements (9:30-11:00
[4 slots of 0h20]) Industry partners from system
companies, SoC providers, and IP providers will express their needs for
methods, tools, interfaces, and standards for pre-silicon debug of complex
multi-core systems. Current practice and available solutions will be discussed,
as well as future directions to be undertaken in research, development, and
standardization. Presenters: ·
LSI Logic – ·
Debug IP for SoC Debug – Mark Woods, ·
Freescale – Robert
Oshana, Freescale, USA ·
SPRINT Debug Working Group –
Requirements from Infineon, ST, NXP on Debug Methods – Michael
Velten, Infineon, Munich, Germany Break and Networking (11:00-11:15 [0h15]) Session 3: Debug Standardisation
Activities
(11:15-12:45 [5 slots of 0h15]) In this session existing active
standardization initiatives will be presented together with their achievements,
roadmaps, current evolution, and industry support. Presenters: ·
OCP Debug Socket for Multicore
Debugging - ·
IEEE Nexus 5001 - ·
SPIRIT IP-XACT Debug WG – ·
POWER.ORG – Chris Ng, ·
IEEE 1687 iJTAG - Stylianos
Diamantidis, Globetech
Solutions & iJTAG 1687 WG ·
Linking the Worlds of SystemC and Eclipse, the GreenSocs VPP Project - Lunch (12:45-13:30
[0h45]) Session 4: Debug Tools &
Implementations Presentations (13:30-15:45 [8 slots 0h15 each]) Available tool solutions will be
introduced in this session, these short (10-15min) presentations will be
followed by demonstrations in the Session 6. Presenters: §
ARM RealView Debug Tools - Mark Woods, §
The Confirma Platform for ASIC,
SoC and IP debug in FPGA - §
Magillem: IP-XACT Flow Control for Debug - §
Post-Silicon System Validation and Debug - §
Flexible Debugging of SoC and IP hardware and System Software on the PROC_SoC Platform - §
Debugging using the SHAPES Virtual
Platform – §
Nexus-5001 Compatible Real-time
Trace for SoC Debug - Akilesh Parameswar, §
CJTAG Block/Chip Level Verification Engine – Stylianos Diamantidis, Globetech Solutions Break (15:45-16:00
[0h15]) Session 5: Panel: Are we
developing right debug solutions to tackle with the real challenges of complex
MP SoCs? (16:00-16:30) The panel will gather opinions from
all industry sectors on possible future evolutions required to enable efficient
SoC debug able to scale to current and future technology. It will discuss the
overlaps in standardization activities that make the entire picture of future
industry proven standards very difficult to draw… Session 6: Demos + Networking (16:30-17:15) This session will enable
parallel demonstrations of EDA tools, free discussion, and networking between
participants of the workshop. More
information: [EMAIL PROTECTED] +33 4 76 63 49
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