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![DASIP2008]()
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Conference on Design
and Architectures
for Signal and Image Processing
DASIP 2008
http://www.ecsi.org/dasip/
Maison Université Libre de Bruxelles, Belgium
November 24-26, 2008 |
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Conference Update!
The conference features 32 high-quality papers and 14 posters that highlight the latest work occurring in the area of design and architectures dedicated to signal and image processing.
More details concerning the DASIP'08 technical program and the registration can be found on the conference website,
http://www.ecsi.org/dasip/
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Keynotes Presentation
AAA Philosophy Applied to Multimedia System on Chip Design
Kristof Denolf (IMEC)
Achieving a cost-efficient implementation of state-of-the-art multimedia requires designing to conform with the triple A philosophy: balancing the Application, Algorithm and Architecture. The main current hurdles are breaking the memory, power and instruction level parallelism wall.
Properly introducing and exploiting parallelization is an important key of the solution to overcome these. This presentation will first give an overview of our current experience with triple A design on a variety of platforms (both on commercially available multi-processor platforms as on an in-house designed MPSoC).
To meet the ever demanding requirements (cost, throughput, processing capabilities and often power) of future applications, like for instance hyper-spectral imaging, future developments will need to further exploit this Triple A philosophy in all its dimensions: heterogeneous design and 3D integration enabling new opportunities, variability/reliability that arise when moving to the latest technology node, etc.
Monday - November 24, 2008 - 10:30-11:30
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Rethinking Embedded Software for Mobile Devices
Johan Eker (Ericsson)
With the introduction of increasingly parallel hardware in the mobile space, established paradigms for embedded software are being challenged. Evolutionary changes of existing methodologies and tools are doomed to fail and the situation calls for new ideas and concepts.
The problem of resource allocation, which is complicated for the uniprocessor case, becomes even more complex with multiple, possibly heterogeneous, cores. Traditionally, systems are carefully tuned by hand for a number of uses. The increasing complexity of mobile handset software, paired with the likewise more complex hardware, makes manual resource allocation infeasible.
A control theoretically sound approach for dynamic resource management is proposed together with a logical view on resource utilization. A dataflow programming model, which allows for explicit parallelism is also discussed.
Tuesday - November 25, 2008 - 9:00-10:00
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Middleware Centric Design for Massively Parallel Stream Processing Platforms
Tapani Ahonen (Tampere University of Technology)
Design space for Digital Signal Processing (DSP) applications is limited by the degree to which the target architecture allows tradeoffs between:
(a) correctness (fault tolerance, dependability)
(b) responsiveness (task deadlines, realtime requirements)
(c) energy consumption (power density, heat sinking, battery lifetime).
The key challenge in designing domain specific or general-purpose application development platforms is to provide trade-off flexibility with low overhead. Most importantly, the required application engineering effort should be kept moderate. Middleware and its application programming interface (API) are in a central role in hiding the management effort required by the added flexibility. The major roles of middleware are: to provide service access mechanisms hiding the details of the
architecture from the application layer, and to autonomously tune the system according to its current state and the function(s) required. The emergence of distributed, massively parallel stream processing architectures calls for novel approaches. Besides efficient communication and resource allocation the platform architectures need to provide middleware-friendly interfaces for monitoring and modifying their state. This presentation highlights the techniques adopted in the EU co-funded
projects: the Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project and the "Silicon Cafe" platform that includes the Cofee CPU.
Wednesday - November 26, 2008 - 9:00-10:00
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