A quick update on ptlsim.

Someone on the ptlsim list pointed out to me that when priming the
cache, one needs to do this *during* the simulator run, not
immediately before, as ptlsim also simulates the caches and has no way
of accessing actual processor caches (or apparently of tracking what
should be in them).

This sped things up considerably. My 11 cycle per limb code now only
take 16.4 cycles per limb on ptlsim.

A guy who works for AMD's open source initiative also mentions that he
has found ptlsim to be off by a bit. His group has a version of ptlsim
called ptlsim/asf which is supposedly better at scheduling accurately.
However a quick look at their website suggests this is designed to
mimic a K10 not a K8.

Bill.

On Nov 28, 3:05 pm, "Bill Hart" <[EMAIL PROTECTED]> wrote:
> No, not at the moment, thanks. There appears to still be an issue with
> it which I have not sorted out. Perhaps it is not as useful as I first
> thought.
>
> Bill.
>
> 2008/11/28 mabshoff <[EMAIL PROTECTED]>:
>
>
>
> > On Nov 27, 8:06 pm, Bill Hart <[EMAIL PROTECTED]> wrote:
>
> > Hi,
>
> >> I got ptlsim working and analysing the addmul_1 code with some help
> >> from an Australian computer science PhD.
>
> > Do you want me to attempt to get it installed anywhere?
>
> >> It's not for the faint hearted!
>
> > It looks very cool. If I did assembly code tuning I would be all over
> > it :)
>
> >> For 1 call to addmul_1 with about 1024 limbs it produces a log file of
> >> 110k lines!!
>
> >> The output is, umm, interesting and contained a number of *very*
> >> interesting surprises. That is probably all I should say. Let's just
> >> say that we have been making some rather fundamental and naive
> >> assumptions.
>
> > :)
>
> >> Bill.
>
> > Cheers,
>
> > Michael
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