Not if it was an intel. I only have AMD machines. On 27 January 2011 08:25, Jason <ja...@njkfrudils.plus.com> wrote: > On Thursday 27 January 2011 06:55:22 Jason wrote: >> On Tuesday 25 January 2011 21:23:21 jason wrote: >> > On Dec 5 2010, 11:01 am, Jason <ja...@njkfrudils.plus.com> wrote: >> > > On Sunday 05 December 2010 07:50:44 Jason wrote: >> > > > On Sunday 05 December 2010 07:05:40 Jason wrote: >> > > > > I've added improved versions for >> > > > > >> > > > > K8 mpn_nand_n >> > > > > K8 mpn_nior_n >> > > > > >> > > > > These run at the optimal 1.5c/l for ALL alignments , whereas the >> > > > > old functions run at 1.7c/l to 2.0c/l for some alignments >> > > > > >> > > > > So now all the K8 logic functions run at 1.5c/l for ALL alignments. >> > > > > >> > > > > Jason >> > > > >> > > > I've copyied the new K8 hamdist into the core2 directory as this >> > > > improves the speed form 6.5c/l to 5.9c/l >> > > > I did both the linux and windows versions >> > > > >> > > > Jason >> > > >> > > A new mpn_store for K8/K10/K102 the old one ran like >> > > >> > > box12 K8 model 44 .75c/l >> > > lena K102 model4 0.5c/l >> > > redhawk K102 model 8 0.75c/l >> > > flavius K8 mode 5 0.75c/l >> > > >> > > and the new one >> > > >> > > box12 K8 model 44 .55c/l >> > > lena K102 model4 0.5c/l >> > > redhawk K102 model 8 0.5c/l >> > > flavius K8 mode 5 0.55c/l >> > > >> > > You can see from the above that the K102 has at least two variants, >> > > looks like they are continually tweaking the design(or fixing it) >> > > >> > > Jason >> > >> > It looks like AMD has just(ish) updated their docs , and we are >> > missing some models AND familys (besides the obvious bobcat and >> > bulldozer). There is some interesting stuff there , including the >> > differences between the revisions , new family 12h with integer >> > hardware fastpath divider ,family 11h,14h , we currently dont >> > recognize any of these , so I think we can release a MPIR_2.2.2 when >> > I've sorted through the variants and I'll check if Intel has updated >> > theirs , and VIA . >> > >> > Jason >> >> For AMD I've added >> >> Family 10h models 5,6,10 as K102 >> >> Family 12h as K102 , we dont have any specific code for the new hardware >> divider >> >> Family 11h as K8 , it's a fusion of K8 core with GPU >> >> Family 14h as K8 , it's a fusion of bobcat core with GPU >> >> to mpir-2.2 and trunk , and I've also added sandybridge as westmere to >> mpir-2.2 >> >> Now to see what Intel and VIA have documented. >> >> The bobcat core has the ABM unit like the K10 (ie popcount and LZCNT) but >> the floating point unit is only 64bit like the K8 , it's also missing >> 3DNOW , and the pipeline/scheduler is completely different. >> >> Family 15h appears to be the Bulldozer core , but it's not been documented >> yet , and wont be out for a while yet. >> >> Jason > > For Intel I've added models 31 and 46 as nehalem and model 47 as westmere and > I've also changed model 30 from westmere to nehalem . The difference between > westmere and nehalem is that westmere is 32nm and nehalem is 45nm , and > depending on marketing AES encryption. This on trunk and mpir-2.2. > > Bill , didn't you have the model 30 ? , I dont completely trust Intel docs :) > > Thanks > Jason > > -- > You received this message because you are subscribed to the Google Groups > "mpir-devel" group. > To post to this group, send email to mpir-devel@googlegroups.com. > To unsubscribe from this group, send email to > mpir-devel+unsubscr...@googlegroups.com. > For more options, visit this group at > http://groups.google.com/group/mpir-devel?hl=en. > >
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