Bill,
You can find the user's guides for the MSP430 processors here:
http://focus.ti.com/docs/analog/catalog/announcements/brc.jhtml?path=templatedata/cm/brc/data/20011218msp430userguides&templateId=1
TI's home page for the MSP430 processor's is here:
http://focus.ti.com/docs/analog/catalog/announcements/brc.jhtml?path=templatedata/cm/brc/data/20011112msp430home2&templateId=1
The instruction word is actually 0x433f, not 0x3f43 (remember, the MSP
is a wrong-
endian, uhh, I meant little-endian processor.) Breaking this down into
the command bit
fields we get:
0100 0011 0 0 11 1111
op- S-reg Ad B/W As D-reg
code
op-code 0100 is "mov". S-reg is r3 (a special purpose constant generator
register),
Ad is 0 (destination is "register mode"), As is 11 which is in
combination with S-reg
r3 means immediate constant 0FFFFh, D-reg is r15. So, 0x433f corresponds to:
mov #0xFFFF,r15
(If I decoded this correctly.) A pop instruction is actually emulated
using the
mov command and has a very similar encoding. The disassembler may be
confused and incorrectly presenting the mov operation as the emulated
pop instruction.
--
Mitch Burghart
Serveron Corporation
Portland OR USA
Bill Knight wrote:
I was looking through the code generated by the compiler
and believe I came across an error in the assembler.
The function being compiled returns a -1 as an error
condition. The assembly code generated by the compiler
produces the following:
mov #llo(-1),r15
However, msp430-objectdump disassembles the elf file as:
12ae: 3f 43 pop r15
I believe 0x3f43 isin fact 'pop r15' and that 'mov #-1,r15'
is 0x3f41. Unfortunately I do not have a good op-code map.
(If someone could e-mail one to me, it would be much
appreciated.)
The sections of the dump file and generated assembly file
are attached.
-Bill Knight
R O SoftWare
