From: Dmitry [mailto:[email protected]] > Stefan, > > well, I checked the web site. thanks. > I actually cannot get through so quickly. > > But I have to make a preliminary decision within a couple of hours. > > The thing I need is a 32 bit counter (28 actually, but 32 looks better :) > which is up/down counter and which counts as: > input is two (50% duty cycly) sequences. > One sequence shifted against other by pi/2. Depending on a > sign of shift the counter should cont either up or down. > > Then I have to transmitt a counter value to cpu via 8 bit bus. > However, the counter should continue work during lathing and > transmission. > > Also, I need an output wich shows up or down counting, input > for latch select, latch address and counter clear. > > Which fpga will you recommend for this and which one will work?
Dimitry, as Harry Lemmens already wrote, the XCR3128XL would be the device that comes to mind. The counter, latch, muxer and quardature frontend should fit easily in there. Since the MSP you use (I assume?) most probably already is a SMD part, the 100 pin and 144 packages shouldn't be a problem. The 144 is even smaller than the 100. I personally haven't worked with the CoolRunners so far (plan to use them with some MSP430s soon), but used many similar parts from AMD/Vantis and now Lattice. Xilinx offers VHDL input for the WebPack, so you should be able to use many open source example designs - just like you would do with 74xxx parts in a conventional design. The people at the mentioned VHDL newsgroup are usually a very nice and helpful gang. If you never used VHDL before, get you a good starting book like "The Designers' Guide to VHDL" written by Peter J. Ashenden (ISBN: 1558606742). HTH, Stefan
