Chris Liechti wrote:
Jens Andersen wrote:
Hi Garst and list,
I have played a little with the fet140_fll2.c example from the
TI fet tools package.
Using a freqency counter the DCO seems rock solid, but my
old Tek 210 dso don't like it, i suppose this has to with jitter.
the DCOLCK signal does have a jitter by design.
it is mixing two frequencies within 32 clocks. one is higher, the
other lower than the target freq, but the mean over 32 clock cycles is
very accurate.
chris
I thought this was true only if MODx is set to something other than 0
and RSEL < 7
Thanks for your time on this issue,
Garst
