Greetings, Processor = MSP430F1232:
I hope this will save someone else from wasting hours finding out that the uart initialization process has some hidden sequence issues. In the code below, if line 220 is commented out, and line 223 is uncommented, then receive interrupts are not enabled. The uart works fine by polling, but doesn't generate interrupts. I guess its a bad habit to think that the last thing one does in an initialization routine is to give the hardware permission to run. 199 ;------------------------------------------------------------------- 200 .global init_uart 201 .equ ME2_INIT,0x03 ;enable transmit and receive 202 .equ U0CTL_INIT,0x10 ;8 bit data, plus defaults 203 .equ U0TCTL_INIT,0x21 ;smclk and set tx empty 204 .equ U0RCTL_INIT,0x0 ;defaults 205 ; 9600 @3.6864MHz 206 .equ U0BR1_INIT,0x01 207 .equ U0BR0_INIT,0x80 208 .equ U0MCTL_INIT,0x00 209 .equ IE2_INIT,0x01 ;allow receive interrupts 210 211 init_uart: 212 ;------------------------------------------------------------------- 213 bis.b #SWRST,&U0CTL ;hold in reset during init 214 bis.b #U0CTL_INIT,&U0CTL 215 bis.b #U0TCTL_INIT,&U0TCTL 216 bis.b #U0RCTL_INIT,&U0RCTL 217 mov.b #U0BR1_INIT,&U0BR1 218 mov.b #U0BR0_INIT,&U0BR0 219 mov.b #U0MCTL_INIT,&U0MCTL 220 bic.b #SWRST,&U0CTL ;let it run 221 bis.b #ME2_INIT,&ME2 222 bis.b #IE2_INIT,&IE2 223 ; bic.b #SWRST,&U0CTL ;let it run 224 ret Sincerely, David Smead www.amplepower.com www.amplepower.net
