Hi Grant,
Ok try this patch.
Its a real hack of the way memory moves work, they are all mov.b
instructions for word (2 byte) moves. I completely understand how all
this works and how best to make changes, but in the examples posted I
think it generates the correct code (although using 6 extra bytes, for
the case where the source or destination of the move are word aligned).
It should leave "; movehiC" and "; movehi" comments in the .s file, if
they are where you want them then I can take them out, see if its
targeting the correct instructions first.
Register moves should be same, and I'm not sure if this is correct or not.
Regards,
--
Peter Jansen
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diff -rU5 gcc-3.2.3-orig/gcc/config/msp430/msp430.c
gcc-3.2.3/gcc/config/msp430/msp430.c
--- gcc-3.2.3-orig/gcc/config/msp430/msp430.c 2006-04-24 02:18:20.000000000
+1000
+++ gcc-3.2.3/gcc/config/msp430/msp430.c 2006-09-13 22:49:35.000000000
+1000
@@ -3546,10 +3546,71 @@
return (-1);
return (REGNO (x));
}
+const char *
+msp430_movehi_code (insn, operands, len)
+ rtx insn;
+ rtx operands[];
+ int *len;
+{
+ rtx op0 = operands[0];
+ rtx op1 = operands[1];
+
+
+ if (memory_operand (op0, VOIDmode)
+ && memory_operand (op1, VOIDmode) && zero_shifted (op1))
+ {
+ if (!len)
+ msp430_emit_indexed_mov2 (insn, operands, NULL);
+ else
+ *len = 3;
+ return "";
+ }
+ else if (register_operand (op0, VOIDmode)
+ && memory_operand (op1, VOIDmode) && zero_shifted (op1))
+ {
+ if (!len)
+ movsisf_regmode (insn, operands, NULL);
+ else
+ *len = 1;
+ return "";
+ }
+
+ if (!len)
+ {
+ if (GET_CODE (operands[1]) == CONST_INT)
+ {
+ output_asm_insn ("mov.b\t#(%F1&0xff), %I0; movehiC", operands);
+ output_asm_insn ("mov.b\t#(%F1>>8), %J0; movehiC", operands);
+ }
+ else
+ {
+ output_asm_insn ("mov.b\t%I1, %I0; movehi", operands);
+ output_asm_insn ("mov.b\t%J1, %J0; movehi", operands);
+ }
+ }
+ else
+ {
+ *len = 1; /* base length */
+
+ if (register_operand (op0, VOIDmode))
+ *len += 0;
+ else if (memory_operand (op0, VOIDmode))
+ *len += 1;
+
+ if (register_operand (op1, VOIDmode))
+ *len += 0;
+ else if (memory_operand (op1, VOIDmode))
+ *len += 1;
+ else if (immediate_operand (op1, VOIDmode))
+ *len += 1;
+ }
+
+ return "";
+}
const char *
msp430_movesi_code (insn, operands, len)
rtx insn;
rtx operands[];
diff -rU5 gcc-3.2.3-orig/gcc/config/msp430/msp430.md
gcc-3.2.3/gcc/config/msp430/msp430.md
--- gcc-3.2.3-orig/gcc/config/msp430/msp430.md 2006-01-30 20:47:05.000000000
+1100
+++ gcc-3.2.3/gcc/config/msp430/msp430.md 2006-09-13 21:25:52.000000000
+1000
@@ -1155,18 +1155,27 @@
[(set (match_operand:HI 0 "nonimmediate_operand_msp430" "")
(match_operand:HI 1 "general_operand_msp430" ""))]
""
"")
-(define_insn "*movhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand_msp430"
"=m,m,m,m,r,r,r,r")
- (match_operand:HI 1 "general_operand_msp430" "
r,m,P,i,r,m,P,i"))]
+(define_insn "*movhi2"
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
+ (match_operand:HI 1 "general_operand_msp430" " r,m,P,i")) ]
""
- "mov\\t%1, %0 "
- [(set_attr "length" "2,3,3,3,1,2,2,2")
+ "mov\\t%1, %0"
+ [(set_attr "length" "1,2,2,2")
(set_attr "cc" "none")])
+(define_insn "*movhi2m"
+ [(set (match_operand:HI 0 "memory_operand_msp430" "=mmmm")
+ (match_operand:HI 1 "general_operand_msp430" " rmPi")) ]
+ ""
+ "* return msp430_movehi_code(insn,operands,NULL);"
+ [(set_attr "length" "3")
+ (set_attr "cc" "none")])
+
+
(define_insn "movhipi"
[(set (match_operand:HI 0 "nonimmediate_operand_msp430" "=r,m")
(mem:HI (post_inc:HI (match_operand:HI 1 "register_operand" "r,r"))))]
""
"mov @%1+, %0"
