It seems I'm the only person taking this seriously - an earlier post was ignored.
The CPU6 bug is a very serious one, documented in TI's slaz020. In summary, any RET or RETI, returning from a function or interrupt call, which hits an add with a register indirect source address, will cause the add to be *executed twice*. TI suggest two possible workarounds. 1. One may avoid the register indirect addressing mode as source address on adds, substituting indexed indirect with zero index. They quite rightly document their concern that an optimisation pass may reverse this. 2. Change the opcode of RETI to an alternate, which works normally, and add a NOP before any error-prone ADD after a CALL. The opcode change seems fairly bulletproof, but an optimiser will surely clobber the NOP. Neither fix is easily done by an mspgcc user, since the fixes must be applied in the libraries as well as in code generated by the user. Theoretically, there exist revision E chips without these bugs, but you can't buy one yet, and even the latest samples from TI are rev. D, which have the bug. In any case, the earlier chips are out there - lots of them. Does anyone have any ideas on how to cope? -- Rick Jenkins <[email protected]> Hartman Technica http://www.hartmantech.com Phone +1 (403) 230-1987 voice & fax 221 35 Avenue. N.E., Calgary, Alberta, Canada T2E 2K5
