Hello,
Using the schematics and firmware of the PySerJTAG interface I
succesfully implemented a serial JTAG interface using a MSP430F1232. I
slightly modified the firmware to support the F1232. Programming another
F1232 using this JTAG interface works fine.
However, my goal was to program a MSP430F2013. As you know, these
processors support Spy-By-Wire. Initially, I do not want to use this, as
this would require significant changes to your firmware. According the
TI datasheet on JTAG programming, the initialization of the 4-wire JTAG
interface on these microprocessors is different ftom the MSP430F1x
processors. It needs a special signal sequence on the TEST and RST pins.
I added support for this to your firmware, but the F2013 processor does
not seem to respond. Programming the other F1232 still works with these
modifications.
To verify the implementation I slowed the signals down using delays of
seconds. Notably, the F1232 processor still responds on the TDO line
with these slow signals (as it should). However, although the
initialization sequence seems to be correct, the F2013 never puts a
signal on the TDO line during the initialization sequence (InitTarget(),
GetDevice()). At normal signal speed, the pyserjtag tool reports 'NACK:
no target', indicating that the intialization failed. In the process I
tried multiple F2013 processors, all with the same result.
On the target board the RST pin has a 10k pull-up and the TEST pin is
pulled down inside the processor. The modifications to the JTAG
initalization are as follows (the original code is commented out):
void InitTarget(void)
{
/* Standard 4-wire JTAG interfaces * /
JTAGSEL = 0x00; // Pins all I/Os
JTAGDIR = TEST; // first enable only test
JTAGOUT = TEST|TDI|TMS|TCK|TCLK|RST;
Delay(2); // small delay until other pins$
JTAGDIR = TEST|TDI|TMS|TCK|TCLK|RST;
*/
/* Spy-By-Wire enabled chips */
JTAGSEL = 0x00;
JTAGDIR = TEST;
JTAGOUT = TEST|TDI|TMS|TCK|TCLK;
Delay(2);
JTAGDIR = TEST|RST;
Delay(2);
JTAGDIR = RST;
Delay(2);
JTAGDIR = TEST|RST;
Delay(2);
JTAGOUT = TEST|TDI|TMS|TCK|TCLK|RST;
Delay(2);
JTAGDIR = TEST|TDI|TMS|TCK|TCLK|RST;
/**/
VPPSEL &= ~(VPPONTDI | VPPONTEST); // No special function, I/Os
VPPOUT &= ~(VPPONTDI | VPPONTEST); // VPPs are OFF
VPPDIR |= (VPPONTDI | VPPONTEST); // VPP pins are outputs
Delay(50); // Settle MOS relays, target $
}
I used many delays, but removing or increasing them seems to have no
effect. The F2013 processor never reponds with a signal on the TDO line.
Do you have any experience with programming the F2013 (or similar)
processors using the Serial JTAG interface or do you see what I am doing
wrong?
Thanks in advance for any help you can provide..
Regards,
Stephan Bosch
PS: If the mspgcc mailinglist is for discussions about the compiler
only, I am sorry for this CC post.
