Thank you Sergey! I have been hoping for 2272 support for a while now, and I'm looking forward to the next release with your patch.
Thanks again! -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Sergey A. Borshch Sent: Friday, August 29, 2008 6:32 AM To: [email protected] Subject: [Mspgcc-users] MSP430X core support in binutils Hi everyone. I almost finished patch, that adds full MSP430X support to binutils 2.18. Patch based on Alpar work I found here: www.c7obs.net/~perinia/mspgcc/mspgcc-430x.tgz, but almost fully reworked. All MSP430X instructions and address modes are supported in assembling and disassembling. I also added support for all missing cpu's (2112, 2122, 2132, 2232, 2252, 2272, 233, 235, 2330, 2350, 2370, E4232, E4242, E4252, E4272, G4250, G4260, G4270, 4351, 4361, 4371, 4783, 4784, 4793, 4794, 5418, 5419, 5435, 5436, 5437, 5438) I found on TI website, fixed some bugs (try to assemble any two-operand instruction without second argument and separating comma or jne without arguments with current version of msp430-as for example) and changed CPU4 bug workaround so it applies only for mcu's that has this bug. I need some time to test if all relocations works correctly, and after that I'll be ready to send my patch to mspgcc patches tracker at sourceforge. Now I have some problems I can't resolve myself, without collective discussion. Problem #1: ld not supports splitted text output section with "hole" for vectors. So we need to link all contents with addresses above 0x10000 to separate output section and memory region. They needs name. Which names we chose for them (fartext, farflash, extflash, maybe other)? The same question about section name for constants in extended address space. The second approach I see is to place .vectors input section into .text output section and discard memory region "vectors" from ld script. I don't know which solution is better and tested only the first one. Problem #2: Extension word for register mode has "Repetition count" field. But I can't find any mentioning of this field in instruction syntax description in User Guide (and in IAR assembler documentation as well). So does it need to be an extra operand, preceding pseudo-op or something else? Problem #3: MSP430, MSP430X(241x, 26x, 46xx) and MSP430X2(5xxx) cores have different instruction timings. Timings are calculated during disassembling (file opcodes/msp430-dis.c, but calculated value not used in main disassembling function print_insn_msp430(). Does we need instruction cycles information in listings (so, we must fix comments output in print_insn_msp430) or not (so, we can remove timing calculations from underlaying functions)? Any suggestion about those problems are welcome. Let's make mspgcc better together. Sergey. ------------------------------------------------------------------------ - This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK & win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100&url=/ _______________________________________________ Mspgcc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/mspgcc-users
