Hi Dmitry, shouldn't you use
#include "msp430x24*1*x.h" instead off #include "msp430x24x.h" Because, you are using an MSP430F24*1*8 Greetings Matthias Dmitry Zuikov schrieb: > On Thu, 2009-04-02 at 16:10 +0200, Roberto Padovani wrote: > > > >> Well, then there is no problem with the __low_level_init, it must be >> something in the UART setup, maybe the PxSEL bits or so... >> > > This is an TI's example. I have only added #include <signal.h> and > changed interrupt handler definition. > > >> However, I am wondering why I had the problem while you don't.....did >> you use a compiler switch to turn off the __low_level_init ? >> > > I even do not how to do it. > > > >> R# >> >> >> >>> The problem also that I probably can't fix this compiler myself even if >>> I found the reason. >>> >>> --- >>> Regards, >>> Dmitry >>> >>> >>> >>>>>> R# >>>>>> >>>>>> 2009/4/1 Dmitry Zuikov <[email protected]>: >>>>>> >>>>>>> Greetings, >>>>>>> >>>>>>> Could anybody provide an assistance (not for free, of course) porting >>>>>>> our application from MSP430F1612 to MSP430F2418 ? >>>>>>> >>>>>>> I faced problems even when I try to launch an example from TI site >>>>>>> adapted for gcc (code is below). >>>>>>> >>>>>>> This code works ok under IAR, but there is no any response in port under >>>>>>> MSPGCC. >>>>>>> >>>>>>> I built mspgcc from cvs. >>>>>>> >>>>>>> code (adapted MSP430x261x_uscia0_uart_03.c ) >>>>>>> //****************************************************************************** >>>>>>> // MSP430x26x Demo - USCI_A0, Ultra-Low Pwr UART 9600 Echo ISR, 32kHz >>>>>>> ACLK >>>>>>> // >>>>>>> // Description: Echo a received character, RX ISR used. Normal mode is >>>>>>> LPM3, >>>>>>> // USCI_A0 RX interrupt triggers TX Echo. >>>>>>> // ACLK = BRCLK = LFXT1 = 32768Hz, MCLK = SMCLK = DCO ~1.045MHz >>>>>>> // Baud rate divider with 32768Hz XTAL @9600 = 32768Hz/9600 = 3.41 >>>>>>> // //* An external watch crystal is required on XIN XOUT for ACLK *// >>>>>>> // >>>>>>> // MSP430F261x/241x >>>>>>> // ----------------- >>>>>>> // /|\| XIN|- >>>>>>> // | | | 32kHz >>>>>>> // --|RST XOUT|- >>>>>>> // | | >>>>>>> // | P3.4/UCA0TXD|------------> >>>>>>> // | | 9600 - 8N1 >>>>>>> // | P3.5/UCA0RXD|<------------ >>>>>>> // >>>>>>> // B. Nisarga >>>>>>> // Texas Instruments Inc. >>>>>>> // September 2007 >>>>>>> // Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: >>>>>>> 3.42A >>>>>>> //****************************************************************************** >>>>>>> #include "msp430x24x.h" >>>>>>> #include <signal.h> >>>>>>> #include <stdlib.h> >>>>>>> >>>>>>> void main(void) >>>>>>> { >>>>>>> WDTCTL = WDTPW + WDTHOLD; // Stop WDT >>>>>>> P3OUT &= ~(BIT4+BIT5); >>>>>>> P3SEL = 0x30; // P3.4,5 = USCI_A0 TXD/RXD >>>>>>> UCA0CTL1 |= UCSSEL_1; // CLK = ACLK >>>>>>> UCA0BR0 = 0x03; // 32kHz/9600 = 3.41 >>>>>>> UCA0BR1 = 0x00; // >>>>>>> UCA0MCTL = UCBRS1 + UCBRS0; // Modulation UCBRSx = 3 >>>>>>> UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state >>>>>>> machine** >>>>>>> IE2 |= UCA0RXIE; // Enable USCI_A0 RX >>>>>>> interrupt >>>>>>> >>>>>>> //eint(); >>>>>>> //__bis_SR_register(LPM3_bits + GIE); // Enter LPM3, interrupts >>>>>>> enabled >>>>>>> for(;;); >>>>>>> } >>>>>>> >>>>>>> // Echo back RXed character, confirm TX buffer is ready first >>>>>>> interrupt ( USCIAB0RX_VECTOR ) wakeup USCI0RX_ISR(void) >>>>>>> { >>>>>>> while (!(IFG2&UCA0TXIFG)); // USCI_A0 TX buffer ready? >>>>>>> UCA0TXBUF = UCA0RXBUF; // TX -> RXed character >>>>>>> } >>>>>>> >>>>>>> >>>>>>> >>>>>>> >>>>>>> ------------------------------------------------------------------------------ >>>>>>> _______________________________________________ >>>>>>> Mspgcc-users mailing list >>>>>>> [email protected] >>>>>>> https://lists.sourceforge.net/lists/listinfo/mspgcc-users >>>>>>> >>>>>>> >>>>>> ------------------------------------------------------------------------------ >>>>>> _______________________________________________ >>>>>> Mspgcc-users mailing list >>>>>> [email protected] >>>>>> https://lists.sourceforge.net/lists/listinfo/mspgcc-users >>>>>> >>>>> ------------------------------------------------------------------------------ >>>>> _______________________________________________ >>>>> Mspgcc-users mailing list >>>>> [email protected] >>>>> https://lists.sourceforge.net/lists/listinfo/mspgcc-users >>>>> >>>>> >>>> ------------------------------------------------------------------------------ >>>> _______________________________________________ >>>> Mspgcc-users mailing list >>>> [email protected] >>>> https://lists.sourceforge.net/lists/listinfo/mspgcc-users >>>> >>> ------------------------------------------------------------------------------ >>> _______________________________________________ >>> Mspgcc-users mailing list >>> [email protected] >>> https://lists.sourceforge.net/lists/listinfo/mspgcc-users >>> >>> >> ------------------------------------------------------------------------------ >> _______________________________________________ >> Mspgcc-users mailing list >> [email protected] >> https://lists.sourceforge.net/lists/listinfo/mspgcc-users >> > > > ------------------------------------------------------------------------------ > _______________________________________________ > Mspgcc-users mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/mspgcc-users > > > >
