We recently switched to the msp430f2618 from a msp430f1611 and on boot up I noticed that DCOCTL was getting zero'd. This occured when I set SVSCTL=0.
On further investigation, I noticed that SVSCTL and DCOCTL were both being set to 0x56. I tracked this down to msp430/include/msp430x261x.h which includes msp430/svs.h but doesn't define __msp430_has_svs_at_0x55. This is an artifact of the evolution of the chips over time. Earlier chips (no DCO, FLL) had the SVS at 56. Those chips are in the x3 and x4 families. I've carefully researched this including looking at how the h/w on the 2618 works and the DCOCTL is at 56 and SVSCTL at 55. There is a typo in the User Guide (slau144e.pdf) for the MSP430x2xx Family. It says that both DCOCTL and SVSCTL are at 56. I've also looked at the data sheet for the MSP430F241x, MSP430F261x (msp430f2618.pdf) and it shows DCOCTL at 56 and SVSCTL at 55. This is also consistent with the x15xx and x161x processors which also have SVS and DCOs. A simple fix would be to add #define __msp430_has_svs_at_0x55 prior to the #include <msp430/svs.h> in msp430x241x.h, msp430x24x1.h, msp430x24x.h, and msp430x261x.h since these cpus all have svs and dco h/w. Who controls the upstream? How does one go about getting changes into the upstream? -- Eric B. Decker Senior (over 50 :-) Researcher
