Hi,
I'm trying to figure out how to make sense of the different msp430 DMA
engines and the way the TI headers (from mspgcc4, Peter Bigot) describe what
is there.
First, here is what I understand about the hardware:
I believe the difference can be distilled down to the following:
SA/DA address size: how many bits are supported in the DMA source and
destination address registers, 16 or 20 bits.
size of the trigger field: The trigger field defines what trigger the DMA
engine uses to start a DMA cycle, can be 4 bits or 5 bits.
DMA_IV: Does the DMA engine interrupt mechanism provide a DMA IV register.
msp430f1611: 16 bit addresses, 4 bit trigger, no dmaiv.
__MSP430_HAS_DMA_3__
msp430f2618: 20 bit addresses, 4 bit trigger, dmaiv.
__MSP430_HAS_MSP430X_CPU__, __MSP430_HAS_DMAX_3__
msp430f5438: 20 bit addresses, 5 bit trigger, dmaiv.
__MSP430_HAS_MSP430XV2__CPU__, __MSP430_HAS_DMAX_3__
Does anyone know a definitive way to determine what kind of dma one has?
I see using (MSP430X_CPU || MSP430XV2_CPU) to tell whether we have 16 or 20
bit addresses. But that is really a CPU thing and not a DMA thing. I
would think that this will also work for nodmaiv vs. dmaiv.
Looks like HAS_DMAX_3 indicates 20 bit addresses and dmaiv.
For 4 bit vs. 5 bit triggers, I can do something like looking for TSEL_31.
If it exists then we have 5 bit otherwise 4 bit.
If possible it would be nice if TI could define functional defines that
describe what kind of DMA engine we have. ie.
__MSP430_DMA_TRIGGER_5BIT__ and/or __MSP430_DMA_TRIGGER_4BIT__
__MSP430_DMA_ADDR_20BIT__ and/or __MSP430_DMA_ADDR_16BIT__
__MSP430_DMAIV__
Is this something reasonable to push towards TI?
thoughts?
eric
--
Eric B. Decker
Senior (over 50 :-) Researcher
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