Hi,
I know what Read-Modify-Write means. At least in the context of non-TI
processors. :-)
I've designed and debugged full blown multiprocessors with nasty snooping
caches.
cache coherency is always entertaining.
Now in the DMA machine for the CC430f5137 and msp430f5438 there is mention
of a DMARMWDIS
bit. (DMACTL4).
Now TI says...
*DMARMWDIS* Bit 2 Read-modify-write disable. When set, this bit inhibits any
DMA transfers from occurring during CPU
read-modify-write operations.
I've looked through the instruction set and nothing jumps out at me as being
a RMW instruction.
So four questions...
1) What does setting DMARMWDIS really do?
2) Is there some mechanism for hooking h/w up in some fashion where one
would need RWM? When
would you need a RMW on one of these systems?
3) Anyone have any idea why TI put this in there? I personally don't see
anyway of hooking things up
in a any fashion where one would need a RMW synchronization primitive. Its
a system on a chip with non-shareable
memory. So WTF?
4) Is there a reasonable forum where one can get a real answer from someone
really in the know at TI?
Now why am I asking? Well I'm currently rewriting a DMA driver that
currently works on a 1611. I'm
rewriting it so it supports the 1611, 2618, and 5438 processors. Same
driver. Minimizes amount of
code needed to be supported.
thanks!!!!
--
Eric B. Decker
Senior (over 50 :-) Researcher
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