Try to look at http://www.national.com/pf/PC/PC8477B.html
It is a FDC from National Semiconductiors.
They seem to have samples.
I have received 7 of these about a year ago.
(they shipped it to the netherlands at no costs for me)
They are PC FDC controllers, but that shouldn't be
a problem.
Greetings from Erik Maas
-----Original Message-----
From: [EMAIL PROTECTED] <[EMAIL PROTECTED]>
To: [EMAIL PROTECTED] <[EMAIL PROTECTED]>
Cc: Walter Bernardo Nunes <[EMAIL PROTECTED]>
Date: vrijdag 19 maart 1999 6:16
Subject: RE: FDC x 1.44Mb
>Marco Antonio Simon dal Poz <[EMAIL PROTECTED]> wrote:
>>Maarten ter Huurne wrote:
>>Do you know a FDC that supports 1.2Mb and 1.44Mb drives and is still being
>>produced, and have good documentation?
I think these docs and ICs are unavailable today.
>>Note that 3.5MHz is too slow to allow reading of 1.44MB disks. The "inner
>>loop" of the sector read routine is too slow to cope with the data flow.
Drivers 1.44MB uses 360 r.p.m. when 720kb uses 300 r.p.m. ?
>> So
>>if you want to create 1.44MB drives for MSX, you either have to use 7MHz
>>Z80 or use some kind of buffer for reading sectors.
>Are you sure? A 720kb disk works with a FDC that handles 250kbits/s, a
>1440kb disk works with a FDC that handles 500kbits/s.
I don't know, but if angular speed is 360 * 2 * PI / 60 ,
that required more CPU speed OR _DMA_ for flow control.
>This means that the
>main routine should be able to read 12500 bytes per turn. It means that
>this routine should run 12500 times in 0.2 seconds. Then, the routine
>should spend a maximum of 16 microseconds. In a 3.57561149MHz, this means
>57 clockcicles.
If I used a trigger for control signal "data available" on
hardware (i.e. waiting for "Wait" signal comes up), avoid
you routine ?
I see possibilities. Control is set on read on D0h port.
Only for information, the correct number of states (T):
> LD HL,address 10T
> LD C,D3h 7T
>LOOP:IN A,(D0h) ; 12 clocks 11T <- Start Loop
> RRCA ; 5 clocks 4T
> JR NC,LOOP ; 9 or 12 clocks 9-12T
> RRCA ; 5 clocks 4T
> RET NC ; 9 clocks 5T
> INI ; 21 clocks 16T
> JP LOOP ; 10 clocks 10T
[Reference: Signectics Z80 family data sheet]
TOTAL 11+4+12+4+5+16+10 = 62 T-cicles if no-wait inserted.
If wait-logic is used, the read routine is:
LD HL, address 10T
LD C, D3h 7T
LOOP:IN A, (D0h) 11T <- WAIT INSERTED (Hardware tests
RRCA 4T data bus D7 )
RRCA 4T
RET NC 5T
INI 16T
JP LOOP 10T
TOTAL 11+4+4+5+16+10 = 50 T-cicles + waits.
>Conclusion: you're right, it's not possible
>to use 1.2Mb or 1.44Mb disks with Z80 at 3.57MHz.
I try to work on this scheme, but I need 1.44M FDC IC.
Who know this IC commercial number ?
MARUJO.
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