29 maggio 2022 09:46, "Stéphane Letz" <l...@grame.fr> wrote:
>> 1. Ciaramella DSP language goes public and open source >> >> ---------------------------------------------------------------------- >> >> Date: Sat, 28 May 2022 08:26:31 +0000 >> From: Stefano D'Angelo <stefano.dang...@orastron.com> >> Subject: Ciaramella DSP language goes public and open source >> >> Hi all (apologies for cross-posting), >> >> I am happy to announce that Orastron (https://www.orastron.com/), the >> company of which I am founder >> and CEO, has released a new and experimental audio DSP programming language >> called Ciaramella and >> its source-to-source compiler called Zampogna under the ISC license. >> >> You can check out the official website (https://ciaramella.dev/) - which >> also contains a web >> playground for trying it out directly in the browser - and read about its >> history and motivation >> here: https://www.orastron.com/blog/ciaramella-smc. The compiler source code >> is available at >> https://github.com/paolomarrone/Zampogna. >> >> We'll also present a scientific paper that describes it in the detail on >> Friday 10th June 2022 at >> the Sound and Music Computing conference in Saint-Etienne, France >> (https://smc22.grame.fr/). >> >> Best regards, >> >> Stefano > > Hi Stefano, > > I read again this old 2009 thread about WDF models in Faust. In case it helps > Dirk Roosenburg wrote > the Faust wdmodels.lib: https://faustlibraries.grame.fr/libs/wdmodels/ with a > video here: > https://faust.grame.fr/community/events/#creating-circuit-bendable-wave-digital-models-of-analog-aud > o-circuits-in-faust-dirk-roosenburg > > Stéphane Hello Stéphane, Thanks for pointing it out. We are aware wdmodels.lib, and indeed have discussed its approach into the upcoming SMC paper. I, at least, was not aware of the video, though, I'll watch it ASAP. Long story short: as far as we understand it, wdmodels.lib works by implying unit delays in the reflected waves (from leaves to root), which is sort of ok except it breaks modularity. E.g., you need to specify b[n] = a[n] for capacitors rather than b[n] = a[n-1]. This probably has more unwanted implications as well, but we have not looked much further. Our conclusion is that in order to guarantee full modularity the scheduling of operations needs to be done as late as possible, certainly after "flattening" the computation graph (or equivalent representation). BTW, if you (and the FAUST team) will be in St Etienne for the SMC we'll be more than glad to have a chat! Best regards, Stefano
