Before you fab it, you might want to put some protection between gate & source to prevent ESD damage since this is a separate PCB and wont have the benefit of surrounding circuity until after it's connected. A large resistor (10meg) across C1 will keep C1 discharged. It's not entirely obvious, but C1 is actually a good form of ESD protection, because it can absorb a fairly decent amount of energy before Vgs rises above a safe level.
The human body model (HBM) for ESD testing is 100pF. If I did my math correctly, a 2kV zap at the input terminals would only produce about 100mV across the gate-source *assuming C1 has low inductance and low ESR*. For the output terminal, there's a parasitic diode in the MOSFET to protect from positive zaps. To protect from negative zaps at the output, I think a reverse-biased diode from Vload to GND would work. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to neonixie-l+unsubscr...@googlegroups.com. To post to this group, send an email to neonixie-l@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/e93da1ee-0d6f-417d-9a1a-ee98a892c1fb%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
