From: Jisheng Zhang <jszh...@marvell.com> Date: Wed, 30 Mar 2016 19:55:21 +0800
> The mvneta is also used in some Marvell berlin family SoCs which may > have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE > usage with L1_CACHE_BYTES. > > And since dma_alloc_coherent() is always cacheline size aligned, so > remove the align checks. > > Signed-off-by: Jisheng Zhang <jszh...@marvell.com> Applied.
