From: Vivien Didelot <vivien.dide...@savoirfairelinux.com> Date: Mon, 18 Jul 2016 20:45:28 -0400
> The Marvell switches registers are organized in distinct internal SMI > devices, such as PHY, Port, Global 1 or Global 2 registers sets. > > Since not all chips support every registers sets or have slightly > differences in them (such as old 88E6060 or new 88E6390 likely to be > supported soon), make the setup code clearer now by removing a few > family checks and adding flags to describe the Global 2 registers map. > > This patchset enables basic STP support and bridging on most chips when > getting rid of a few inconsistencies in chip descriptions (patch 1) and > add bridge Ageing Time support to DSA and the mv88e6xxx driver. Series applied.
