On 9/9/2016, Sergei Shtylyov wrote:
> > sh_eth_private *mdp) {
> > if (sh_eth_is_rz_fast_ether(mdp)) {
> > sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
> > + sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
> > + TSU_FWSLC); /* Enable POST registers */
> > return;
> > }
>
> Wait, don't you also need to write 0s to the POST registers like done
> at the end of this function?
Nope.
The sh_eth_chip_reset() function will write to register ARSTR which will do a
HW reset on the block and clear all the registers, including all the POST
registers.
static struct sh_eth_cpu_data r7s72100_data = {
.chip_reset = sh_eth_chip_reset,
So, before sh_eth_tsu_init() is ever called, the hardware will always be reset.
/* initialize first or needed device */
if (!devno || pd->needs_init) {
if (mdp->cd->chip_reset)
mdp->cd->chip_reset(ndev);
if (mdp->cd->tsu) {
/* TSU init (Init only)*/
sh_eth_tsu_init(mdp);
}
}
Therefore there is no reason to set the POST registers back to 0 because they
are already at 0 from the reset.
Chris
