Hi, > We didn't get any ppc64 with PCI-E to run Linux so far. What performance > drop should we expect with our current code ?
We have seen > 20% improvement on ppc64 running some networking workloads when forcing 128 byte alignment (instead of 16 byte alignment). DMA writes have to get cacheline aligned (in power of 2 steps) on some IO chips. > I am not sure what you mean. > The only ppc64 with PCI-E that we have seen so far (a G5) couldn't do > write combining according to Apple. Im thinking more generally, MTRRs are x86 specific and it would be good to have a more generic way to enable write combining. Anton - To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
