From: David Miller
> Sent: 17 January 2017 19:16
> > Relax ordering(RO) is one feature of 82599 NIC, to enable this feature can
> > enhance the performance for some cpu architecure, such as SPARC and so on.
> > Currently it only supports one special cpu architecture(SPARC) in 82599
> > driver to enable RO feature, this is not very common for other cpu
> > architecture
> > which really needs RO feature.
> > This patch add one common config CONFIG_ARCH_WANT_RELAX_ORDER to set RO
> > feature,
> > and should define CONFIG_ARCH_WANT_RELAX_ORDER in sparc Kconfig firstly.
> >
> > Signed-off-by: Mao Wenan <maowe...@huawei.com>
>
> Since no-one has reviewed this patch, and I do not feel comfortable with
> applying
> it without such review, I am tossing this patch.
>
> If someone eventually reviews it, repost this patch.
Having re-read parts of the PCIe spec I think I'd like someone to
explain exactly which transfers are affected by the 'relaxed ordering'
bit and why any re-ordered transactions aren't a problem.
In particular I believe RO allows the write to update the receive
descriptor ring to overtake a write of receive packet data.
That could lead to the network stack processing a receive frame
before it has actually been written.
David
