From: Tom Lendacky <thomas.lenda...@amd.com> Date: Wed, 22 Mar 2017 17:25:27 -0500
> The ECC bit positions that describe whether the ECC interrupt is for > Tx, Rx or descriptor memory and whether the it is a single correctable > or double detected error were defined in incorrectly (reversed order). > Fix the bit position definitions for these settings so that the proper > ECC handling is performed. > > Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com> > --- > > Please queue this patch up for 4.10-stable. Applied and queued up for -stable, thanks.
