Hello Thomas
On 3/21/2017 3:50 PM, Thomas Petazzoni wrote:
Hello,
On Thu, 9 Mar 2017 15:56:31 +0100, Giuseppe CAVALLARO wrote:
On 3/9/2017 10:32 AM, Thomas Petazzoni wrote:
OK, I'll have a look. However, I'm still confused by this DMA_RESET bit
that never clears, contrary to what the datasheet says. Are there some
erratas?
I suggest you to take a look at the tx/rx clocks from PHY.
You have to provide these otherwise you cannot reset the engine.
Thanks for the hint.
you are welcome
Further research has revealed that everything is working fine on a
platform with a Gigabit PHY connected via GMII.
However, on a different platform (which I'm using) with a 10/100 PHY
connected via MII, DMA_RESET never clears, and networking doesn't work.
The SMSC PHY LAN8700 is also supposed to be providing the clock through
its TX_CLK pin. I double checked, and both the MAC and PHY are in MII
mode, but still no luck so far.
Of course, if you have any suggestion or hint, I'm all ears :)
I can just you to keep the focus on clock configuration. I tested the
SMSC PHY LAN8700
w/o any issues on several platform. In MII both rx/tx_clk are provided
by PHY and if you
have an external oscillator this should be safe enough, indeed.
Another check you can do is about the reset time! Maybe you need to
change something
when reset the SMSC transceiver, try to increase the delay (if you use
GPIO to reset it).
Regards
Peppe
Thanks,
Thomas
