On 7/21/17 8:29 AM, Marc Gonzalez wrote:
I don't understand what you're saying.
It is a correct observation that the code enabling
RGMII RX clock delay is a NOP, since that bit will
always be set at that point.
The spec for the 8035 (I haven't checked for 8030 and 8031,
is that what you meant by "other systems"?) states that
Sel_clk125m_dsp, which is described as:
"Control bit for rgmii interface rx clock delay"
is 1 after HW reset, 1 after SW reset.
So my statement "RX clock delay is enabled at reset"
is universally true. It's not just on some systems.
Ok, taken out of context, the comment doesn't really explain why the
code is the way it is. I'm not really happy about the word "assumes".
Maybe you should add a sentence explaining when the code is NOT a no-op.
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