On 11/17/17 3:56 AM, Wang Dongsheng wrote:
-#define TPD_BUFFER_ADDR_H_SET(tpd, val) BITS_SET((tpd)->word[3], 18,
30, val)
+#define TPD_BUFFER_ADDR_H_SET(adpt, tpd, val) BITS_SET((tpd)->word[3], 18, \
+ TX_TS_ENABLE & \
+ readl((adpt)->csr + EMAC_EMAC_WRAPPER_CSR1) ? \
+ 30 : 31, val)
NAK.
Sorry, but this is terrible. Every write to the TPD forces a secret
read from another register? No thank you.
Just do what you had in v1, but also set the DMA mask. Add a comment
saying that we can support 46 bits because we never enable timestamping.
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