On Sat, 2006-09-09 at 07:46 +1000, Benjamin Herrenschmidt wrote: > The PowerPC writel has a full sync _after_ the write, mostly to prevent > it from leaking out of a spinlock, and for ordering it vs. other > writel's or readl's. It doesn't provide any ordering guarantee vs > cacheable storage (and was never intended to do so afaik). Such ordering > shall > be provided explicitely. It's possible that 2.4 used a big hammer > approach but we've since been actively fixing drivers for that. It's to > be noted that PowerPC might not be the only architecture affected as I > don't think that in general, you have ordering guarantees between > cacheable and non-cacheable stores unless you use explicit barriers.
I think 2.4 might have an additional sync before the write which will guarantee that the buffer descriptor is written before telling the chip to DMA it. > > Thus I disagree with "fixing" the powerpc writel(). The barries shall > definitely go into tg3. > You'll have to take this up with David. - To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
