From: Niklas Cassel <niklas.cas...@axis.com> Date: Thu, 8 Mar 2018 11:30:05 +0100
> These wmb() memory barriers are performed after the last descriptor write, > and they are followed by enable_dma_transmission()/set_tx_tail_ptr(), > i.e. a writel() to MMIO register space. > Since writel() itself performs the equivalent of a wmb() before doing the > actual write, these barriers are superfluous, and removing them should > thus not change any existing behavior. > > Ordering within the descriptor writes is already ensured with dma_wmb() > barriers inside prepare_tx_desc(first, ..)/prepare_tso_tx_desc(first, ..). > > Signed-off-by: Niklas Cassel <niklas.cas...@axis.com> Please allow me some time to consider this issue a little bit more before applying this patch. Thank you Niklas.
