On 12/08/2018 06:35 PM, Florian Fainelli wrote: > Le 12/7/18 à 8:25 PM, Marek Vasut a écrit : >> On 12/08/2018 01:52 AM, tristram...@microchip.com wrote: >>>> - padlen = (skb->len >= ETH_ZLEN) ? 0 : ETH_ZLEN - skb->len; >>>> + padlen = (skb->len >= VLAN_ETH_ZLEN) ? 0 : VLAN_ETH_ZLEN - skb- >>>>> len; >>> >>> The requirement is the tail tag should be at the end of frame before FCS. >>> When the length is less than 60 the MAC controller will pad the frame to >>> legal size. That is why this function makes sure the padding is done >>> manually. Increasing the size just increases the length of the frame and >>> the >>> chance to allocate new socket buffer. >>> >>> Example of using ping size of 18 will have the sizes of request and response >>> differ by 4 bytes. Not that it matters much. >>> >>> Are you concerned the MAC controller will remove the VLAN tag and so the >>> frame >>> will not be sent? Or the switch removes the VLAN tag and is not able to >>> send? >> >> With TI CPSW in dual-ethernet configuration, which adds internal VLAN >> tag at the end of the frame, the KSZ switch fails. The CPU will send out >> packets and the switch will reject them as corrupted. It needs this >> extra VLAN tag padding. > > Oh so they add the internal VLAN at the end of the frame, not the > beginning? That is quite surprising but that would not be the one single > oddity found with CPSW I am afraid.. The way I would approach this is > with layering where the padding needs to occur: > > - within the tag driver you need to make sure there is enough room to > insert the KSZ tag > > - within the ethernet MAC driver (which comes last in the transmit > path), you need to make sure there is enough room to insert that trailer > VLAN tag to permit internal transmission
So you think this is a bug in the CPSW instead ? -- Best regards, Marek Vasut
