Hi! > > > > I'm trying to create support for Marvell 88e6065 switch... and it > > > > seems like drivers/net/dsa supports everything, but this model. > > > > > > > > Did someone work with this hardware before? Any idea if it would be > > > > more suitable to support by existing 88e6060 code, or if 88e6xxx code > > > > should serve as a base? > > > > > > Hi Pavel > > > > > > The 88e6xxx should be extended to support this. I think you will find > > > a lot of the building blocks are already in the driver. Compare the > > > various implementations of the functions in the mv88e6xxx_ops to what > > > the datasheet says for the registers, and pick those that match. > > > > Ok, so I played a bit. > > > > It looks like e6065 has different register layout from those supported > > by 6xxx, and is quite similar to e6060. > > However, if you look in the mv88e6xxx, there are quite a few functions > called mv88e6065_foo. Marvell keeps changing the register layout. When > writing code, we try to name the functions based on which family of > devices introduced those registers. But we don't have the whole > history, so we probably have some names wrong.
Ok, so I took a long look at mv88e6xxx... and got it to work.
Good news is that modifications needed are not too heavy. Most are
inlined below. (tag_daddr is still needed. I can send that too).
Bad news is that only about half of all the registers are present on
6065 (6060 is similar), and I'm not sure how to do that
cleanly. Anything marked "W" is not present or reserved or different
in 6065. What would be good markup of registers that are common to all
and that are newer-generations-only be? Mark everything not present on
6065 as MV88E6085_*?
Is someone is interested in getting 6060 to work with mv88e6xxx?
Best regards,
Pavel
commit b0a8ed2459b8bc1922441edb482d0c7a4217eb1f
Author: Pavel Machek <pa...@denx.de>
Date: Mon Jan 28 15:12:30 2019 +0100
6xxx: Add basic support for 6065.
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 33e99dfa00a8..0a1fc2432094 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -2094,6 +2094,21 @@ static int mv88e6xxx_set_port_mode_edsa(struct
mv88e6xxx_chip *chip, int port)
ETH_P_EDSA);
}
+static int mv88e6xxx_set_port_mode_header(struct mv88e6xxx_chip *chip, int
port)
+{
+ u16 reg;
+ int err;
+
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
+ if (err)
+ return err;
+
+ reg |= MV88E6XXX_PORT_CTL0_HEADER;
+ printk("port %d -- enabling header, val %lx\n", port, (unsigned long)
reg);
+
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
+}
+
static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
{
if (dsa_is_dsa_port(chip->ds, port))
@@ -2109,6 +2124,11 @@ static int mv88e6xxx_setup_port_mode(struct
mv88e6xxx_chip *chip, int port)
if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
return mv88e6xxx_set_port_mode_edsa(chip, port);
+ if (chip->info->tag_protocol == DSA_TAG_PROTO_DADDR)
+ return mv88e6xxx_set_port_mode_header(chip, port);
+
+ dev_warn(chip->dev, "set port mode failed");
+
return -EINVAL;
}
@@ -2126,6 +2146,7 @@ static int mv88e6xxx_setup_egress_floods(struct
mv88e6xxx_chip *chip, int port)
/* Upstream ports flood frames with unknown unicast or multicast DA */
flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
+ flood = 1; /* This is strange, but original driver also sets flood
everywhere */
if (chip->info->ops->port_set_egress_floods)
return chip->info->ops->port_set_egress_floods(chip, port,
flood, flood);
@@ -3777,7 +3798,58 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
.phylink_validate = mv88e6390x_phylink_validate,
};
+static const struct mv88e6xxx_ops mv88e6065_ops = {
+ /* MV88E6XXX_FAMILY_6095 */ /* Here */
+ //.ieee_pri_map = mv88e6085_g1_ieee_pri_map, /* FIXME */
+ // .ip_pri_map = mv88e6085_g1_ip_pri_map, /* FIXME */
+ // .set_switch_mac = mv88e6xxx_g1_set_switch_mac, /* FIXME */
+ .phy_read = mv88e6185_phy_ppu_read,
+ .phy_write = mv88e6185_phy_ppu_write,
+ .port_set_link = mv88e6xxx_port_set_link, /* ok */
+ .port_set_duplex = mv88e6xxx_port_set_duplex, /* ok */
+ .port_set_speed = mv88e6065_port_set_speed, /* ok */
+ .port_set_frame_mode = mv88e6065_port_set_frame_mode, // -- definitely
not compatible on 6065; neccessary for correct operation? */
+ .port_set_egress_floods = mv88e6352_port_set_egress_floods, /* ok */
+ //.port_set_upstream_port = mv88e6095_port_set_upstream_port, /* FIXME
*/
+ .port_link_state = mv88e6352_port_link_state, /* FIXME -- this one is
wrong, 6065 uses dufferebt bits */
+ //.port_get_cmode = mv88e6185_port_get_cmode, /* FIXME -- wrong bits */
+ //.stats_snapshot = mv88e6xxx_g1_stats_snapshot, /* FIXME */
+ //.stats_set_histogram = mv88e6095_g1_stats_set_histogram, /* FIXME */
+ //.stats_get_sset_count = mv88e6095_stats_get_sset_count, /* FIXME */
+ //.stats_get_strings = mv88e6095_stats_get_strings, /* FIXME */
+ //.stats_get_stats = mv88e6095_stats_get_stats, /* FIXME */
+ //.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, /* FIXME */
+ //.ppu_enable = mv88e6185_g1_ppu_enable, /* FIXME */
+ //.ppu_disable = mv88e6185_g1_ppu_disable, /* FIXME */
+ .reset = NULL, /* No reset bit in global1: register 4, but we have
MV88E6065_G1_RESET */
+ .vtu_getnext = mv88e6185_g1_vtu_getnext, /* ok? */
+ .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, /* FIXME */
+ .phylink_validate = mv88e6065_phylink_validate,
+};
+
static const struct mv88e6xxx_info mv88e6xxx_table[] = {
+ [MV88E6065] = {
+ .prod_num = 0x650,
+ .family = MV88E6XXX_FAMILY_6065,
+ .name = "Marvell 88E6065 not so hacked :-)",
+ .num_databases = 16,
+ .num_ports = 6,
+ .num_internal_phys = 6,
+ .max_vid = 4095,
+ .port_base_addr = 0x18,
+ .phy_base_addr = 0x10,
+ .global1_addr = 0x1f,
+ .global2_addr = 0,
+ .age_time_coeff = 15000,
+ .g1_irqs = 8,
+ .g2_irqs = 0,
+ .atu_move_port_mask = 0xf,
+ .pvt = false,
+ .multi_chip = true,
+ .tag_protocol = DSA_TAG_PROTO_DADDR,
+ .ops = &mv88e6065_ops,
+ },
+
[MV88E6085] = {
.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
.family = MV88E6XXX_FAMILY_6097,
diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
index fc82085d4296..7d6c746d4b66 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -57,10 +57,12 @@ enum mv88e6xxx_frame_mode {
MV88E6XXX_FRAME_MODE_DSA,
MV88E6XXX_FRAME_MODE_PROVIDER,
MV88E6XXX_FRAME_MODE_ETHERTYPE,
+ MV88E6XXX_FRAME_MODE_HEADER,
};
/* List of supported models */
enum mv88e6xxx_model {
+ MV88E6065,
MV88E6085,
MV88E6095,
MV88E6097,
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 3f43c231f40b..cfa16b5fd41a 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -631,6 +631,31 @@ int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip
*chip, int port,
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
}
+int mv88e6065_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
+ enum mv88e6xxx_frame_mode mode)
+{
+ int err;
+ u16 reg;
+
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
+ if (err)
+ return err;
+
+ reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
+
+ switch (mode) {
+ case MV88E6XXX_FRAME_MODE_NORMAL:
+ /* FIXME ... ? why is it needed */
+ reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
+ break;
+ default:
+ printk("Bad frame mode\n");
+ return -EINVAL;
+ }
+
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
+}
+
int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
enum mv88e6xxx_frame_mode mode)
{
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
commit 58a8b67092027331b83311e5621e12870fef0845
Author: Pavel Machek <pa...@denx.de>
Date: Mon Jan 28 14:59:36 2019 +0100
6xxx: headers-only: anotate same and different registers on 6065.
diff --git a/drivers/net/dsa/mv88e6xxx/global1.h
b/drivers/net/dsa/mv88e6xxx/global1.h
index 5df4fc049733..6d7c7868f7d8 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.h
+++ b/drivers/net/dsa/mv88e6xxx/global1.h
@@ -18,15 +18,15 @@
#include "chip.h"
/* Offset 0x00: Switch Global Status Register */
-#define MV88E6XXX_G1_STS 0x00
-#define MV88E6352_G1_STS_PPU_STATE 0x8000
-#define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
-#define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
-#define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
-#define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
-#define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
-#define MV88E6XXX_G1_STS_INIT_READY 0x0800
-#define MV88E6XXX_G1_STS_IRQ_AVB 8
+#define MV88E6XXX_G1_STS 0x00 /* ok */
+#define MV88E6352_G1_STS_PPU_STATE 0x8000
+#define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000 W /* not
on 6065 */
+#define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000 W
+#define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000 W
+#define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000 W
+#define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000 W
+#define MV88E6XXX_G1_STS_INIT_READY 0x0800 /* ok */
+#define MV88E6XXX_G1_STS_IRQ_AVB 8 /* ok vv */
#define MV88E6XXX_G1_STS_IRQ_DEVICE 7
#define MV88E6XXX_G1_STS_IRQ_STATS 6
#define MV88E6XXX_G1_STS_IRQ_VTU_PROB 5
@@ -34,13 +34,13 @@
#define MV88E6XXX_G1_STS_IRQ_ATU_PROB 3
#define MV88E6XXX_G1_STS_IRQ_ATU_DONE 2
#define MV88E6XXX_G1_STS_IRQ_TCAM_DONE 1
-#define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
+#define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0 /* ok ^^ */
/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
* Offset 0x02: Switch MAC Address Register Bytes 2 & 3
* Offset 0x03: Switch MAC Address Register Bytes 4 & 5
*/
-#define MV88E6XXX_G1_MAC_01 0x01
+#define MV88E6XXX_G1_MAC_01 0x01 /* ok */
#define MV88E6XXX_G1_MAC_23 0x02
#define MV88E6XXX_G1_MAC_45 0x03
@@ -57,13 +57,13 @@
/* Offset 0x04: Switch Global Control Register */
#define MV88E6XXX_G1_CTL1 0x04
-#define MV88E6XXX_G1_CTL1_SW_RESET 0x8000
-#define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x4000
-#define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000
-#define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800
-#define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400
-#define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200
-#define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080
+#define MV88E6XXX_G1_CTL1_SW_RESET 0x8000 W /* Not on 6065 */
+#define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x4000 W /* Not on 6065 */
+#define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000 /* ok */
+#define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800 /* ok */
+#define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400 /* ok */
+#define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200 /* ok */
+#define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080 /* ?? vv */
#define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040
#define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020
#define MV88E6XXX_G1_CTL1_VTU_DONE_EN 0x0010
@@ -74,24 +74,24 @@
/* Offset 0x05: VTU Operation Register */
#define MV88E6XXX_G1_VTU_OP 0x05
-#define MV88E6XXX_G1_VTU_OP_BUSY 0x8000
-#define MV88E6XXX_G1_VTU_OP_MASK 0x7000
-#define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000
+#define MV88E6XXX_G1_VTU_OP_BUSY 0x8000 /* ok */
+#define MV88E6XXX_G1_VTU_OP_MASK 0x7000 /* ok */
+#define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000 /* ok vv */
#define MV88E6XXX_G1_VTU_OP_NOOP 0x2000
#define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE 0x3000
-#define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x4000
-#define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x5000
-#define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x6000
-#define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION 0x7000
-#define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION BIT(6)
-#define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION BIT(5)
-#define MV88E6XXX_G1_VTU_OP_SPID_MASK 0xf
+#define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x4000 /* ok ^^ */
+#define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x5000 W /* reserved on 6065 */
+#define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x6000 W /* reserved on 6065 */
+#define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION 0x7000 /* ok */
+#define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION BIT(6) /* ok */
+#define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION BIT(5) /* ok */
+#define MV88E6XXX_G1_VTU_OP_SPID_MASK 0xf /* ok */
/* Offset 0x06: VTU VID Register */
#define MV88E6XXX_G1_VTU_VID 0x06
#define MV88E6XXX_G1_VTU_VID_MASK 0x0fff
-#define MV88E6390_G1_VTU_VID_PAGE 0x2000
-#define MV88E6XXX_G1_VTU_VID_VALID 0x1000
+#define MV88E6390_G1_VTU_VID_PAGE 0x2000 W /* not on 6065 */
+#define MV88E6XXX_G1_VTU_VID_VALID 0x1000 /* ok */
/* Offset 0x07: VTU/STU Data Register 1
* Offset 0x08: VTU/STU Data Register 2
@@ -99,7 +99,7 @@
*/
#define MV88E6XXX_G1_VTU_DATA1 0x07
#define MV88E6XXX_G1_VTU_DATA2 0x08
-#define MV88E6XXX_G1_VTU_DATA3 0x09
+#define MV88E6XXX_G1_VTU_DATA3 0x09 W /* reserved on
6065 */
#define MV88E6XXX_G1_VTU_STU_DATA_MASK 0x0003
#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x0000
#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED 0x0001
@@ -113,12 +113,12 @@
/* Offset 0x0A: ATU Control Register */
#define MV88E6XXX_G1_ATU_CTL 0x0a
#define MV88E6065_G1_RESET 0x8000
-#define MV88E6XXX_G1_ATU_CTL_LEARN2ALL 0x0008
+#define MV88E6XXX_G1_ATU_CTL_LEARN2ALL 0x0008 W /* reserved bit */
/* Offset 0x0B: ATU Operation Register */
#define MV88E6XXX_G1_ATU_OP 0x0b
-#define MV88E6XXX_G1_ATU_OP_BUSY 0x8000
-#define MV88E6XXX_G1_ATU_OP_MASK 0x7000
+#define MV88E6XXX_G1_ATU_OP_BUSY 0x8000 /* ok */
+#define MV88E6XXX_G1_ATU_OP_MASK 0x7000 /* ok vv */
#define MV88E6XXX_G1_ATU_OP_NOOP 0x0000
#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL 0x1000
#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC 0x2000
@@ -126,18 +126,18 @@
#define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB 0x4000
#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB 0x5000
#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB 0x6000
-#define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION 0x7000
+#define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION 0x7000
#define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION BIT(7)
#define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION BIT(6)
#define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION BIT(5)
-#define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION BIT(4)
+#define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION BIT(4) /* ok ^^ */
/* Offset 0x0C: ATU Data Register */
#define MV88E6XXX_G1_ATU_DATA 0x0c
-#define MV88E6XXX_G1_ATU_DATA_TRUNK 0x8000
+#define MV88E6XXX_G1_ATU_DATA_TRUNK 0x8000 /* ??? */
#define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK 0x00f0
#define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
-#define MV88E6XXX_G1_ATU_DATA_STATE_MASK 0x000f
+#define MV88E6XXX_G1_ATU_DATA_STATE_MASK 0x000f /* ok */
#define MV88E6XXX_G1_ATU_DATA_STATE_UNUSED 0x0000
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_MGMT 0x000d
#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC 0x000e
@@ -151,7 +151,7 @@
* Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
* Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
*/
-#define MV88E6XXX_G1_ATU_MAC01 0x0d
+#define MV88E6XXX_G1_ATU_MAC01 0x0d /* ok */
#define MV88E6XXX_G1_ATU_MAC23 0x0e
#define MV88E6XXX_G1_ATU_MAC45 0x0f
@@ -164,7 +164,7 @@
* Offset 0x16: IP-PRI Mapping Register 6
* Offset 0x17: IP-PRI Mapping Register 7
*/
-#define MV88E6XXX_G1_IP_PRI_0 0x10
+#define MV88E6XXX_G1_IP_PRI_0 0x10 /* ok */
#define MV88E6XXX_G1_IP_PRI_1 0x11
#define MV88E6XXX_G1_IP_PRI_2 0x12
#define MV88E6XXX_G1_IP_PRI_3 0x13
@@ -174,10 +174,10 @@
#define MV88E6XXX_G1_IP_PRI_7 0x17
/* Offset 0x18: IEEE-PRI Register */
-#define MV88E6XXX_G1_IEEE_PRI 0x18
+#define MV88E6XXX_G1_IEEE_PRI 0x18 /* ok */
/* Offset 0x19: Core Tag Type */
-#define MV88E6185_G1_CORE_TAG_TYPE 0x19
+#define MV88E6185_G1_CORE_TAG_TYPE 0x19 W /* reserved on 6065 */
/* Offset 0x1A: Monitor Control */
#define MV88E6185_G1_MONITOR_CTL 0x1a
@@ -188,8 +188,8 @@
#define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK 0x000f
/* Offset 0x1A: Monitor & MGMT Control Register */
-#define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a
-#define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000
+#define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a /* ok */
+#define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000 W /* not
on 6065 */
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK 0x3f00
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO 0x0000
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI 0x0100
@@ -198,10 +198,10 @@
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100
#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000
-#define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff
+#define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff
W /* different on 6065 ? */
/* Offset 0x1C: Global Control 2 */
-#define MV88E6XXX_G1_CTL2 0x1c
+#define MV88E6XXX_G1_CTL2 0x1c W /* different, mostly
reserved on 6065 */
#define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000
#define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000
#define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000
@@ -230,11 +230,11 @@
#define MV88E6390_G1_CTL2_HIST_MODE_TX 0x0080
#define MV88E6352_G1_CTL2_CTR_MODE_MASK 0x0060
#define MV88E6390_G1_CTL2_CTR_MODE 0x0020
-#define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f
+#define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f W /* reserved on 6065 */
/* Offset 0x1D: Stats Operation Register */
#define MV88E6XXX_G1_STATS_OP 0x1d
-#define MV88E6XXX_G1_STATS_OP_BUSY 0x8000
+#define MV88E6XXX_G1_STATS_OP_BUSY 0x8000 /* ok */
#define MV88E6XXX_G1_STATS_OP_NOP 0x0000
#define MV88E6XXX_G1_STATS_OP_FLUSH_ALL 0x1000
#define MV88E6XXX_G1_STATS_OP_FLUSH_PORT 0x2000
@@ -242,14 +242,14 @@
#define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT 0x5000
#define MV88E6XXX_G1_STATS_OP_HIST_RX 0x0400
#define MV88E6XXX_G1_STATS_OP_HIST_TX 0x0800
-#define MV88E6XXX_G1_STATS_OP_HIST_RX_TX 0x0c00
+#define MV88E6XXX_G1_STATS_OP_HIST_RX_TX 0x0c00 /* ok */
#define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9 0x0200
#define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 0x0400
/* Offset 0x1E: Stats Counter Register Bytes 3 & 2
* Offset 0x1F: Stats Counter Register Bytes 1 & 0
*/
-#define MV88E6XXX_G1_STATS_COUNTER_32 0x1e
+#define MV88E6XXX_G1_STATS_COUNTER_32 0x1e /* ok */
#define MV88E6XXX_G1_STATS_COUNTER_01 0x1f
int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
diff --git a/drivers/net/dsa/mv88e6xxx/global2.h
b/drivers/net/dsa/mv88e6xxx/global2.h
index 48e501d15e20..f5a52b7bfb12 100644
--- a/drivers/net/dsa/mv88e6xxx/global2.h
+++ b/drivers/net/dsa/mv88e6xxx/global2.h
@@ -18,7 +18,7 @@
#include "chip.h"
/* Offset 0x00: Interrupt Source Register */
-#define MV88E6XXX_G2_INT_SRC 0x00 /* FIXME: reserved */
+#define MV88E6XXX_G2_INT_SRC 0x00 W /* reserved */
#define MV88E6XXX_G2_INT_SRC_WDOG 0x8000
#define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000
#define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000
@@ -30,7 +30,7 @@
#define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15
/* Offset 0x01: Interrupt Mask Register */
-#define MV88E6XXX_G2_INT_MASK 0x01 /* FIXME: reserved */
+#define MV88E6XXX_G2_INT_MASK 0x01 W /* reserved */
#define MV88E6XXX_G2_INT_MASK_WDOG 0x8000
#define MV88E6XXX_G2_INT_MASK_JAM_LIMIT 0x4000
#define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x2000
@@ -40,16 +40,16 @@
#define MV88E6390_G2_INT_MASK_PHY 0x07fe
/* Offset 0x02: MGMT Enable Register 2x */
-#define MV88E6XXX_G2_MGMT_EN_2X 0x02 /* FIXME: reserved */
+#define MV88E6XXX_G2_MGMT_EN_2X 0x02 W /* reserved */
/* Offset 0x03: MGMT Enable Register 0x */
-#define MV88E6XXX_G2_MGMT_EN_0X 0x03 /* FIXME: reserved */
+#define MV88E6XXX_G2_MGMT_EN_0X 0x03 W /* reserved */
/* Offset 0x04: Flow Control Delay Register */
-#define MV88E6XXX_G2_FLOW_CTL 0x04 /* FIXME: reserved */
+#define MV88E6XXX_G2_FLOW_CTL 0x04 W /* reserved */
/* Offset 0x05: Switch Management Register */
-#define MV88E6XXX_G2_SWITCH_MGMT 0x05 /* FIXME: reserved
*/
+#define MV88E6XXX_G2_SWITCH_MGMT 0x05 W /* reserved */
#define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000
#define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000
#define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000
@@ -57,7 +57,7 @@
#define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008
/* Offset 0x06: Device Mapping Table Register */
-#define MV88E6XXX_G2_DEVICE_MAPPING 0x06 /* FIXME: reserved */
+#define MV88E6XXX_G2_DEVICE_MAPPING 0x06 W /* reserved */
#define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000
#define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00
#define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK 0x000f
@@ -70,7 +70,7 @@
#define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800
/* Offset 0x08: Trunk Mapping Table Register */
-#define MV88E6XXX_G2_TRUNK_MAPPING 0x08 /* FIXME: reserved */
+#define MV88E6XXX_G2_TRUNK_MAPPING 0x08 W /* reserved */
#define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000
#define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800
@@ -94,11 +94,11 @@
#define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f
/* Offset 0x0A: Ingress Rate Data Register */
-#define MV88E6XXX_G2_IRL_DATA 0x0a
+#define MV88E6XXX_G2_IRL_DATA 0x0a /* ok */
#define MV88E6XXX_G2_IRL_DATA_MASK 0xffff
/* Offset 0x0B: Cross-chip Port VLAN Register */
-#define MV88E6XXX_G2_PVT_ADDR 0x0b
+#define MV88E6XXX_G2_PVT_ADDR 0x0b W /* reserved */
#define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000
#define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000
#define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000
@@ -107,11 +107,11 @@
#define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff
/* Offset 0x0C: Cross-chip Port VLAN Data Register */
-#define MV88E6XXX_G2_PVT_DATA 0x0c
+#define MV88E6XXX_G2_PVT_DATA 0x0c W /* reserved */
#define MV88E6XXX_G2_PVT_DATA_MASK 0x7f
/* Offset 0x0D: Switch MAC/WoL/WoF Register */
-#define MV88E6XXX_G2_SWITCH_MAC 0x0d
+#define MV88E6XXX_G2_SWITCH_MAC 0x0d W /* reserved */
#define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000
#define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00
#define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff
@@ -120,7 +120,7 @@
#define MV88E6XXX_G2_ATU_STATS 0x0e
/* Offset 0x0F: Priority Override Table */
-#define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f
+#define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f W /* reserved */
#define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000
#define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000
#define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00
@@ -130,7 +130,7 @@
#define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007
/* Offset 0x14: EEPROM Command */
-#define MV88E6XXX_G2_EEPROM_CMD 0x14
+#define MV88E6XXX_G2_EEPROM_CMD 0x14 W /* reserved */
#define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000
#define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000
#define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000
@@ -142,15 +142,15 @@
#define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff
/* Offset 0x15: EEPROM Data */
-#define MV88E6352_G2_EEPROM_DATA 0x15
+#define MV88E6352_G2_EEPROM_DATA 0x15 W /* reserved */
#define MV88E6352_G2_EEPROM_DATA_MASK 0xffff
/* Offset 0x15: EEPROM Addr */
-#define MV88E6390_G2_EEPROM_ADDR 0x15
+#define MV88E6390_G2_EEPROM_ADDR 0x15 W /* reserved */
#define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff
/* Offset 0x16: AVB Command Register */
-#define MV88E6352_G2_AVB_CMD 0x16
+#define MV88E6352_G2_AVB_CMD 0x16 W /* reserved */
#define MV88E6352_G2_AVB_CMD_BUSY 0x8000
#define MV88E6352_G2_AVB_CMD_OP_READ 0x4000
#define MV88E6352_G2_AVB_CMD_OP_READ_INCR 0x6000
@@ -173,10 +173,10 @@
#define MV88E6352_G2_AVB_CMD_ADDR_MASK 0x001f
/* Offset 0x17: AVB Data Register */
-#define MV88E6352_G2_AVB_DATA 0x17
+#define MV88E6352_G2_AVB_DATA 0x17 W /* reserved */
/* Offset 0x18: SMI PHY Command Register */
-#define MV88E6XXX_G2_SMI_PHY_CMD 0x18
+#define MV88E6XXX_G2_SMI_PHY_CMD 0x18 W /* reserved */
#define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000
#define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000
#define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000
@@ -197,16 +197,16 @@
#define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff
/* Offset 0x19: SMI PHY Data Register */
-#define MV88E6XXX_G2_SMI_PHY_DATA 0x19
+#define MV88E6XXX_G2_SMI_PHY_DATA 0x19 W /* reserved */
/* Offset 0x1A: Scratch and Misc. Register */
-#define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a
+#define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a W /* reserved */
#define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000
#define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00
#define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff
/* Offset 0x1B: Watch Dog Control Register */
-#define MV88E6352_G2_WDOG_CTL 0x1b
+#define MV88E6352_G2_WDOG_CTL 0x1b W /* reserved */
#define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080
#define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040
#define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020
@@ -217,7 +217,7 @@
#define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001
/* Offset 0x1B: Watch Dog Control Register */
-#define MV88E6390_G2_WDOG_CTL 0x1b
+#define MV88E6390_G2_WDOG_CTL 0x1b W /* reserved */
#define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000
#define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00
#define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000
@@ -232,14 +232,14 @@
#define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001
/* Offset 0x1C: QoS Weights Register */
-#define MV88E6XXX_G2_QOS_WEIGHTS 0x1c
+#define MV88E6XXX_G2_QOS_WEIGHTS 0x1c W /* reserved */
#define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000
#define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00
#define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00
#define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff
/* Offset 0x1D: Misc Register */
-#define MV88E6XXX_G2_MISC 0x1d
+#define MV88E6XXX_G2_MISC 0x1d W /* reserved */
#define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000
#define MV88E6352_G2_NOEGR_POLICY 0x2000
#define MV88E6390_G2_LAG_ID_4 0x2000
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index f32f56af8e35..5b9dde5c3334 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -19,13 +19,13 @@
/* Offset 0x00: Port Status Register */
#define MV88E6XXX_PORT_STS 0x00
-#define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
+#define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000 /* ok vvv */
#define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
-#define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
+#define MV88E6XXX_PORT_STS_HD_FLOW 0x2000 W /* "link mode is
resolved" on 6065 */
#define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
-#define MV88E6XXX_PORT_STS_LINK 0x0800
-#define MV88E6XXX_PORT_STS_DUPLEX 0x0400
-#define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300
+#define MV88E6XXX_PORT_STS_LINK 0x0800 W /* -- 0x1000
on 6065? */
+#define MV88E6XXX_PORT_STS_DUPLEX 0x0400 W /* -- 0x200 on 6065*/
+#define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300 W /* -- mask is 0x0f00
on 6065 */
#define MV88E6XXX_PORT_STS_SPEED_10 0x0000
#define MV88E6XXX_PORT_STS_SPEED_100 0x0100
#define MV88E6XXX_PORT_STS_SPEED_1000 0x0200
@@ -33,38 +33,38 @@
#define MV88E6352_PORT_STS_EEE 0x0040
#define MV88E6165_PORT_STS_AM_DIS 0x0040
#define MV88E6185_PORT_STS_MGMII 0x0040
-#define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020
-#define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010
-#define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f
-#define MV88E6XXX_PORT_STS_CMODE_100BASE_X 0x0008
-#define MV88E6XXX_PORT_STS_CMODE_1000BASE_X 0x0009
-#define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a
-#define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b
-#define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c
-#define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d
-#define MV88E6185_PORT_STS_CDUPLEX 0x0008
-#define MV88E6185_PORT_STS_CMODE_MASK 0x0007
-#define MV88E6185_PORT_STS_CMODE_GMII_FD 0x0000
-#define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS 0x0001
-#define MV88E6185_PORT_STS_CMODE_MII_100 0x0002
-#define MV88E6185_PORT_STS_CMODE_MII_10 0x0003
-#define MV88E6185_PORT_STS_CMODE_SERDES 0x0004
-#define MV88E6185_PORT_STS_CMODE_1000BASE_X 0x0005
-#define MV88E6185_PORT_STS_CMODE_PHY 0x0006
-#define MV88E6185_PORT_STS_CMODE_DISABLED 0x0007
+#define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020 /* ok */
+#define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010 /* ok */
+#define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f W /* vv these are
reserved or different */
+#define MV88E6XXX_PORT_STS_CMODE_100BASE_X 0x0008 W
+#define MV88E6XXX_PORT_STS_CMODE_1000BASE_X 0x0009 W
+#define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a W
+#define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b W
+#define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c W
+#define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d W
+#define MV88E6185_PORT_STS_CDUPLEX 0x0008 W
+#define MV88E6185_PORT_STS_CMODE_MASK 0x0007 W
+#define MV88E6185_PORT_STS_CMODE_GMII_FD 0x0000 W
+#define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS 0x0001 W
+#define MV88E6185_PORT_STS_CMODE_MII_100 0x0002 W
+#define MV88E6185_PORT_STS_CMODE_MII_10 0x0003 W
+#define MV88E6185_PORT_STS_CMODE_SERDES 0x0004 W
+#define MV88E6185_PORT_STS_CMODE_1000BASE_X 0x0005 W
+#define MV88E6185_PORT_STS_CMODE_PHY 0x0006 W
+#define MV88E6185_PORT_STS_CMODE_DISABLED 0x0007 W /* ^^ */
/* Offset 0x01: MAC (or PCS or Physical) Control Register */
#define MV88E6XXX_PORT_MAC_CTL 0x01
-#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000
-#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000
-#define MV88E6185_PORT_MAC_CTL_SYNC_OK 0x4000
-#define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000
-#define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000
-#define MV88E6352_PORT_MAC_CTL_200BASE 0x1000
-#define MV88E6185_PORT_MAC_CTL_AN_EN 0x0400
-#define MV88E6185_PORT_MAC_CTL_AN_RESTART 0x0200
-#define MV88E6185_PORT_MAC_CTL_AN_DONE 0x0100
-#define MV88E6XXX_PORT_MAC_CTL_FC 0x0080
+#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000 W /* vv reserved
*/
+#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000 W
+#define MV88E6185_PORT_MAC_CTL_SYNC_OK 0x4000 W
+#define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000 W
+#define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000 W
+#define MV88E6352_PORT_MAC_CTL_200BASE 0x1000 W
+#define MV88E6185_PORT_MAC_CTL_AN_EN 0x0400 W
+#define MV88E6185_PORT_MAC_CTL_AN_RESTART 0x0200 W /* ^^ reserved
*/
+#define MV88E6185_PORT_MAC_CTL_AN_DONE 0x0100 W /* reserved on
6065 */
+#define MV88E6XXX_PORT_MAC_CTL_FC 0x0080 /* ok vv */
#define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040
#define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020
#define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010
@@ -76,15 +76,15 @@
#define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002
#define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002
#define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003
-#define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003
+#define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003 /* ok ^^ */
/* Offset 0x02: Jamming Control Register */
-#define MV88E6097_PORT_JAM_CTL 0x02
+#define MV88E6097_PORT_JAM_CTL 0x02 W /* Not on 6065 */
#define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00
#define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff
/* Offset 0x02: Flow Control Register */
-#define MV88E6390_PORT_FLOW_CTL 0x02
+#define MV88E6390_PORT_FLOW_CTL 0x02 W
#define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000
#define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00
#define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000
@@ -92,8 +92,10 @@
#define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff
/* Offset 0x03: Switch Identifier Register */
-#define MV88E6XXX_PORT_SWITCH_ID 0x03
+#define MV88E6XXX_PORT_SWITCH_ID 0x03 /* ok */
#define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6035 0x0350 /* very similar to 6065
*/
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6065 0x0650
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990
@@ -124,132 +126,133 @@
/* Offset 0x04: Port Control Register */
#define MV88E6XXX_PORT_CTL0 0x04
-#define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000
-#define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK 0x4000
-#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000
+#define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000 W /* not
on 6065, unused */
+#define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK 0x4000 /*
...but this matches? */
+#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000 /* ok,
matches 6065 */
#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000
#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000
#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000
-#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000
-#define MV88E6XXX_PORT_CTL0_HEADER 0x0800
-#define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400
-#define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200
+#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000 W /* not
on 6065, unused */
+#define MV88E6XXX_PORT_CTL0_HEADER 0x0800 /* ok,
matches 6065 */
+#define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400 /* ok */
+#define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200 W /* not
on 6065, unused */
#define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300
#define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000
-#define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100
-#define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200
+#define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100
+#define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200
W /* not on 6065, not used */
#define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300
-#define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100
-#define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080
-#define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040
-#define MV88E6185_PORT_CTL0_USE_IP 0x0020
-#define MV88E6185_PORT_CTL0_USE_TAG 0x0010
+#define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100 W /* not
on 6065, unused */
+#define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080
/* ok */
+#define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040
/* ok */
+#define MV88E6185_PORT_CTL0_USE_IP 0x0020 /* ok */
+#define MV88E6185_PORT_CTL0_USE_TAG 0x0010 /* ok */
#define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004
-#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK 0x000c
+#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK 0x000c /* ok */
#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA 0x0000
#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA 0x0004
#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA 0x0008
#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA 0x000c
-#define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003
+#define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003 /* ok */
#define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000
#define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001
#define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002
#define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003
/* Offset 0x05: Port Control 1 */
-#define MV88E6XXX_PORT_CTL1 0x05
+#define MV88E6XXX_PORT_CTL1 0x05 W /* undocumented /
reserved */
#define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000
#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff
/* Offset 0x06: Port Based VLAN Map */
#define MV88E6XXX_PORT_BASE_VLAN 0x06
-#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000
+#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000 W /* 6065 has dbum there
*/
+/* ...and more bits below */
/* Offset 0x07: Default Port VLAN ID & Priority */
#define MV88E6XXX_PORT_DEFAULT_VLAN 0x07
-#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff
+#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff /* ok */
/* Offset 0x08: Port Control 2 Register */
#define MV88E6XXX_PORT_CTL2 0x08
-#define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000
+#define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000 /* ok vv */
#define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000
#define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000
-#define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000
-#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000
-#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000
-#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000
-#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000
-#define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00
+#define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000 /* ok ?? */
+#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000 W /* vv:
incompatible */
+#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000 W
+#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000 W
+#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000 W /* ^^ */
+#define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00 /* ok vv */
#define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000
#define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400
#define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800
#define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00
#define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200
#define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100
-#define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080
-#define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040
-#define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020
-#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010
-#define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f
+#define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080 /* ok %% */
+#define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040 W /* reserved on
6065 */
+#define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020 W /* reserved on
6065 */
+#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010 W /* reserved on
6065 */
+#define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f W /* 6065 has
qpri overrides here */
/* Offset 0x09: Egress Rate Control */
-#define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09
+#define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09 W /* we have
ingress control here */
/* Offset 0x0A: Egress Rate Control 2 */
-#define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a
+#define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a W /* so this may
not be compatible */
/* Offset 0x0B: Port Association Vector */
#define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b
-#define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000
-#define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000
-#define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000
-#define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000
-#define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800
+#define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000 W /* 6065 is
different -- Ingress monitor */
+#define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000 W /*
portsched on 6065 */
+#define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000 /* ok */
+#define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000 /* ok */
+#define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800 W /* 6065 has
agenten */
/* Offset 0x0C: Port ATU Control */
-#define MV88E6XXX_PORT_ATU_CTL 0x0c
+#define MV88E6XXX_PORT_ATU_CTL 0x0c W /* not on 6065? */
/* Offset 0x0D: Priority Override Register */
-#define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d
+#define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d W /* not on 6065? */
/* Offset 0x0E: Policy Control Register */
-#define MV88E6XXX_PORT_POLICY_CTL 0x0e
+#define MV88E6XXX_PORT_POLICY_CTL 0x0e W /* not on 6065? */
/* Offset 0x0F: Port Special Ether Type */
-#define MV88E6XXX_PORT_ETH_TYPE 0x0f
+#define MV88E6XXX_PORT_ETH_TYPE 0x0f W /* not on 6065? */
#define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100
/* Offset 0x10: InDiscards Low Counter */
-#define MV88E6XXX_PORT_IN_DISCARD_LO 0x10
+#define MV88E6XXX_PORT_IN_DISCARD_LO 0x10 W /* different counter on 6065 */
/* Offset 0x11: InDiscards High Counter */
-#define MV88E6XXX_PORT_IN_DISCARD_HI 0x11
+#define MV88E6XXX_PORT_IN_DISCARD_HI 0x11 W /* different counter on 6065 */
/* Offset 0x12: InFiltered Counter */
-#define MV88E6XXX_PORT_IN_FILTERED 0x12
+#define MV88E6XXX_PORT_IN_FILTERED 0x12 W /* ok, depending on other bit? */
/* Offset 0x13: OutFiltered Counter */
-#define MV88E6XXX_PORT_OUT_FILTERED 0x13
+#define MV88E6XXX_PORT_OUT_FILTERED 0x13 W /* not on 6065 */
/* Offset 0x18: IEEE Priority Mapping Table */
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18
-#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000
-#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000
-#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000
-#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000
-#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000
-#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000
-#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000
-#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000
-#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000
-#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00
-#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000 W /*
reserved on 6065 */
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000 W
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000 W
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000 W
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000 W
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000 W
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000 W
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000 W
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000 W
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00 W
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff W /* ^^
looks different on 6065 */
/* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */
-#define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18
+#define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18 W
/* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */
-#define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19
+#define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19 W
int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
u16 *val);
@@ -289,6 +292,8 @@ int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip,
int port);
int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
enum mv88e6xxx_egress_mode mode);
+int mv88e6065_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
+ enum mv88e6xxx_frame_mode mode);
int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
enum mv88e6xxx_frame_mode mode);
int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
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