On Fri, Jun 05, 2020 at 07:10:58PM +0100, Jonathan McDowell wrote: > The QCA8337(N) has an SGMII port which can operate in MAC, PHY or BASE-X > mode depending on what it's connected to (e.g. CPU vs external PHY or > SFP). At present the driver does no configuration of this port even if > it is selected. > > Add support for making sure the SGMII is enabled if it's in use, and > device tree support for configuring the connection details.
Hi Jonathan It is good to include Russell King in Cc: for patches like this. Also, netdev is closed at the moment, so please post patches as RFC. It sounds like the hardware has a PCS which can support SGMII or 1000BaseX. phylink will tell you what mode to configure it to. e.g. A fibre SFP module will want 1000BaseX. A copper SFP module will want SGMII. A switch is likely to want 1000BaseX. A PHY is likely to want SGMII. So remove the "sgmii-mode" property and configure it as phylink is requesting. What exactly does sgmii-delay do? > +#define QCA8K_REG_SGMII_CTRL 0x0e0 > +#define QCA8K_SGMII_EN_PLL BIT(1) > +#define QCA8K_SGMII_EN_RX BIT(2) > +#define QCA8K_SGMII_EN_TX BIT(3) > +#define QCA8K_SGMII_EN_SD BIT(4) > +#define QCA8K_SGMII_CLK125M_DELAY BIT(7) > +#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23)) > +#define QCA8K_SGMII_MODE_CTRL_BASEX 0 > +#define QCA8K_SGMII_MODE_CTRL_PHY BIT(22) > +#define QCA8K_SGMII_MODE_CTRL_MAC BIT(23) I guess these are not really bits. You cannot combine QCA8K_SGMII_MODE_CTRL_MAC and QCA8K_SGMII_MODE_CTRL_PHY. So it makes more sense to have: #define QCA8K_SGMII_MODE_CTRL_BASEX (0x0 << 22) #define QCA8K_SGMII_MODE_CTRL_PHY (0x1 << 22) #define QCA8K_SGMII_MODE_CTRL_MAC (0x2 << 22) Andrew