From: "Michael Chan" <[EMAIL PROTECTED]>
Date: Fri, 23 Mar 2007 16:13:07 -0800
> [TG3]: Exit irq handler during chip reset.
>
> On most tg3 chips, the memory enable bit in the PCI command register
> gets cleared during chip reset and must be restored before accessing
> PCI registers using memory cycles. The chip does not generate
> interrupt during chip reset, but the irq handler can still be called
> because of irq sharing or irqpoll. Reading a register in the irq
> handler can cause a master abort in this scenario and may result in a
> crash on some architectures.
>
> Use the TG3_FLAG_CHIP_RESETTING flag to tell the irq handler to exit
> without touching any registers. The checking of the flag is in the
> "slow" path of the irq handler and will not affect normal performance.
> The msi handler is not shared and therefore does not require checking
> the flag.
>
> Thanks to Bernhard Walle <[EMAIL PROTECTED]> for reporting the problem.
>
> Signed-off-by: Michael Chan <[EMAIL PROTECTED]>
Applied, except I fixed up some weird tabbing on this line:
> @@ -3568,32 +3568,34 @@ static irqreturn_t tg3_interrupt(int irq, void
> *dev_id)
...
> + } else {
> + /* No work, shared interrupt perhaps? re-enable
> + * interrupts, and flush that PCI write
> + */
> + tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
> + 0x00000000);
^^^^^^^^
There are two tabs, some space characters, then a final tab,
and it doesn't even make the argument match up to the openning
parenthesis on the previous line :-)
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