On Tue, Aug 18, 2020 at 03:14:08PM +0800, Landen Chao wrote:
> Add a structure holding required operations for each device such as device
> initialization, PHY port read or write, a checker whether PHY interface is
> supported on a certain port, MAC port setup for either bus pad or a
> specific PHY interface.
>
> The patch is done for ready adding a new hardware MT7531.
>
> Signed-off-by: Landen Chao <landen.c...@mediatek.com>
> Signed-off-by: Sean Wang <sean.w...@mediatek.com>
> ---
> drivers/net/dsa/mt7530.c | 272 +++++++++++++++++++++++++++++----------
> drivers/net/dsa/mt7530.h | 37 +++++-
> 2 files changed, 240 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
> index 0fd50798aa42..d30b41725b4d 100644
> --- a/drivers/net/dsa/mt7530.c
> +++ b/drivers/net/dsa/mt7530.c
> @@ -372,8 +372,9 @@ mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
> mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
> }
>
> +/* Setup TX circuit incluing relevant PAD and driving */
> static int
> -mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
> +mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
> {
> struct mt7530_priv *priv = ds->priv;
> u32 ncpo1, ssc_delta, trgint, i, xtal;
> @@ -387,7 +388,7 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
> return -EINVAL;
> }
>
> - switch (mode) {
> + switch (interface) {
> case PHY_INTERFACE_MODE_RGMII:
> trgint = 0;
> /* PLL frequency: 125MHz */
Do you actually need to support all 4 RGMII modes?
...
+ goto unsupported;
> + break;
> + case 6: /* 1st cpu port */
> + if (state->interface != PHY_INTERFACE_MODE_RGMII &&
> + state->interface != PHY_INTERFACE_MODE_TRGMII)
phy_interface_mode_is_rgmii()?
Andrew
