Hi, On Mon, Nov 23, 2020 at 04:52:40PM +0200, stef...@marvell.com wrote: > From: Stefan Chulski <stef...@marvell.com> > > Tx/Rx FIFO is a HW resource limited by total size, but shared > by all ports of same CP110 and impacting port-performance. > Do not divide the FIFO for ports which are not enabled in DTS, > so active ports could have more FIFO. > > The active port mapping should be done in probe before FIFO-init.
It would be nice to know what the effect is from this - is it a small or large boost in performance? What is the effect when the ports on a CP110 are configured for 10G, 1G, and 2.5G in that order, as is the case on the Macchiatobin board? Thanks. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
