On Wed, Jan 27, 2021 at 06:41:32PM +0000, Stefan Chulski wrote: > > > > > > From: Stefan Chulski <stef...@marvell.com> > > > > > > RXQ non occupied descriptor threshold would be used by Flow Control > > > Firmware feature to move to the XOFF mode. > > > RXQ non occupied threshold would change interrupt cause that polled by > > > CM3 Firmware. > > > Actual non occupied interrupt masked and won't trigger interrupt. > > > > Does this mean that this change enables a feature, but it is unused due to a > > masked interrupt? > > Firmware poll RXQ non occupied cause register to indicate if number of > registers bellow threshold. > We do not trigger any interrupt, just poll this bit in CM3. So this cause > always masked.
The functional spec for A8040 says that the register at 0xF2005520 is "RX Exceptions Interrupt Mask" and the bit description talks about it controlling interrupt signal generation. However, the bit that allows RX Exceptions to be raised in MVPP2_ISR_RX_TX_MASK_REG is clear, so it won't proceed beyond the next level up. So, I think the commit description needs to say something like: "The firmware needs to monitor the RX Non-occupied descriptor bits for flow control to move to XOFF mode. These bits need to be unmasked to be functional, but they will not raise interrupts as we leave the RX exception summary bit in MVPP2_ISR_RX_TX_MASK_REG clear." I think that's essentially what you're trying to describe - please change if not. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
