I figured out the registers. There is a fence/sync mechanism which apparently triggers after rendering is finished. There are two ways to use it, but they trigger at the same time (spinning in a loop on the CPU checking them, they trigger at the same iteration or in two successive iterations).
The first is the "sync" notifier, which involves a notifier object set at NV40TCL_DMA_NOTIFY. When NV40TCL_NOTIFY, with argument 0, followed by NV40TCL_NOP, with argument 0 is inserted in the ring, the notifier object will be notified when rendering is finished. fbcon uses this to sync rendering. Currently the Mesa driver sets an object but does not use it. The renouveau traces use this mechanism only in the EXT_framebuffer_object tests. It's not clear what the purpose of the NOP is, but it seems necessary. The second is the fence mechanism, which involves an object set at NV40TCL_DMA_FENCE. When register 0x1d70 is set, the value set there will be written to the object at the offset programmed in 0x1d6c. The offset in 0x1d6c must be 16-byte aligned, but the GPU seems to only write 4 bytes with the sequence number. Nouveau does not use this currently, and sets NV40TCL_DMA_FENCE to 0. The nVidia driver uses this often. It allocates a 4KB object and asks the GPU to put the sequence number always at offset 0x5c0. Why it does this rather than allocating a 16 byte object and using offset 0 is unknown. IMHO the fence mechanism should be implemented in the kernel along with the current FIFO fencing, and should protect the relocated buffer object. _______________________________________________ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau