From: Martin Peres <martin.pe...@ensi-bourges.fr>
v2: Reclock memory after reclocking the other engines
Signed-off-by: Martin Peres <martin.pe...@ensi-bourges.fr>
---
drivers/gpu/drm/nouveau/nouveau_pm.c | 11 +--
drivers/gpu/drm/nouveau/nouveau_pms.h | 98 +++++++++++++++++++++
drivers/gpu/drm/nouveau/nv50_pm.c | 153
++++++++++++++++++++++++++++++---
3 files changed, 242 insertions(+), 20 deletions(-)
create mode 100644 drivers/gpu/drm/nouveau/nouveau_pms.h
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c
b/drivers/gpu/drm/nouveau/nouveau_pm.c
index 88f58b1..44d01bb 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.c
@@ -45,10 +45,6 @@ nouveau_pm_clock_set(struct drm_device *dev,
struct nouveau_pm_level *perflvl,
if (khz == 0)
return 0;
- /* Do no reclock the memory if the frequencies didn't change */
- if (id == PLL_MEMORY && pm->cur->memory == khz)
- return 0;
-
pre_state = pm->clock_pre(dev, perflvl, id, khz);
if (IS_ERR(pre_state))
return PTR_ERR(pre_state);
@@ -100,7 +96,6 @@ nouveau_pm_perflvl_set(struct drm_device *dev,
struct nouveau_pm_level *perflvl)
nouveau_pm_clock_set(dev, perflvl, PLL_CORE, perflvl->core);
nouveau_pm_clock_set(dev, perflvl, PLL_SHADER, perflvl->shader);
- nouveau_pm_clock_set(dev, perflvl, PLL_MEMORY, perflvl->memory);
nouveau_pm_clock_set(dev, perflvl, PLL_UNK05, perflvl->unk05);
/* Decrease the voltage if needed*/
@@ -110,11 +105,13 @@ nouveau_pm_perflvl_set(struct drm_device *dev,
struct nouveau_pm_level *perflvl)
/* Wait for PLLs to stabilize */
udelay(100);
+ pm->unpause(dev);
+
+ nouveau_pm_clock_set(dev, perflvl, PLL_MEMORY, perflvl->memory);
+
pm->cur = perflvl;
ret = 0;
- pm->unpause(dev);
-
NV_DEBUG(dev, "Reclocking took %lluns\n",
(nv04_timer_read(dev) - start));
diff --git a/drivers/gpu/drm/nouveau/nouveau_pms.h
b/drivers/gpu/drm/nouveau/nouveau_pms.h
new file mode 100644
index 0000000..d7a445b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_pms.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person
obtaining a
+ * copy of this software and associated documentation files (the
"Software"),
+ * to deal in the Software without restriction, including without
limitation
+ * the rights to use, copy, modify, merge, publish, distribute,
sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom
the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#ifndef __NOUVEAU_PMS_H__
+#define __NOUVEAU_PMS_H__
+
+struct pms_ucode {
+ u8 data[256];
+ union {
+ u8 *u08;
+ u16 *u16;
+ u32 *u32;
+ } ptr;
+ u16 len;
+
+ u32 reg;
+ u32 val;
+};
+
+static inline void
+pms_init(struct pms_ucode *pms)
+{
+ pms->ptr.u08 = pms->data;
+ pms->reg = 0xffffffff;
+ pms->val = 0xffffffff;
+}
+
+static inline void
+pms_fini(struct pms_ucode *pms)
+{
+ do {
+ *pms->ptr.u08++ = 0x7f;
+ pms->len = pms->ptr.u08 - pms->data;
+ } while (pms->len & 3);
+ pms->ptr.u08 = pms->data;
+}
+
+static inline void
+pms_unkn(struct pms_ucode *pms, u8 v0)
+{
+ *pms->ptr.u08++ = v0;
+}
+
+static inline void
+pms_op5f(struct pms_ucode *pms, u8 v0, u8 v1)
+{
+ *pms->ptr.u08++ = 0x5f;
+ *pms->ptr.u08++ = v0;
+ *pms->ptr.u08++ = v1;
+}
+
+static inline void
+pms_wr32(struct pms_ucode *pms, u32 reg, u32 val)
+{
+ if (val != pms->val) {
+ if ((val & 0xffff0000) == (pms->val & 0xffff0000)) {
+ *pms->ptr.u08++ = 0x42;
+ *pms->ptr.u16++ = (val & 0x0000ffff);
+ } else {
+ *pms->ptr.u08++ = 0xe2;
+ *pms->ptr.u32++ = val;
+ }
+
+ pms->val = val;
+ }
+
+ if ((reg & 0xffff0000) == (pms->reg & 0xffff0000)) {
+ *pms->ptr.u08++ = 0x40;
+ *pms->ptr.u16++ = (reg & 0x0000ffff);
+ } else {
+ *pms->ptr.u08++ = 0xe0;
+ *pms->ptr.u32++ = reg;
+ }
+ pms->reg = reg;
+}
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c
b/drivers/gpu/drm/nouveau/nv50_pm.c
index 4dd2d76..9b81f03 100644
--- a/drivers/gpu/drm/nouveau/nv50_pm.c
+++ b/drivers/gpu/drm/nouveau/nv50_pm.c
@@ -26,9 +26,11 @@
#include "nouveau_drv.h"
#include "nouveau_bios.h"
#include "nouveau_pm.h"
+#include "nouveau_pms.h"
struct nv50_pm_state {
struct nouveau_pm_level *perflvl;
+ struct pms_ucode ucode;
struct pll_lims pll;
enum pll_types type;
int N, M, P;
@@ -73,14 +75,20 @@ void *
nv50_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level
*perflvl,
u32 id, int khz)
{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nv50_pm_state *state;
- int dummy, ret;
+ struct pms_ucode *pms;
+ u32 reg0_old, reg0_new;
+ u32 crtc_mask;
+ u32 reg_c040;
+ int ret, dummy, i;
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return ERR_PTR(-ENOMEM);
state->type = id;
state->perflvl = perflvl;
+ pms = &state->ucode;
ret = get_pll_limits(dev, id, &state->pll);
if (ret < 0) {
@@ -95,20 +103,88 @@ nv50_pm_clock_pre(struct drm_device *dev, struct
nouveau_pm_level *perflvl,
return ERR_PTR(ret);
}
+ reg0_old = nv_rd32(dev, state->pll.reg + 0);
+ reg0_new = 0x80000000 | (state->P << 16) | (reg0_old & 0xfff8ffff);
+
+ reg_c040 = nv_rd32(dev, 0xc040);
+
+ crtc_mask = 0;
+ for (i = 0; i < 2; i++) {
+ if (nv_rd32(dev, NV50_PDISPLAY_CRTC_C(i, CLOCK)))
+ crtc_mask |= (1 << i);
+ }
+
+ pms_init(pms);
+
+ switch (state->type) {
+ case PLL_MEMORY:
+ /* Wait for vblank on all the CRTCs */
+ if (crtc_mask) {
+ pms_op5f(pms, crtc_mask, 0x00);
+ pms_op5f(pms, crtc_mask, 0x01);
+ }
+
+ pms_wr32(pms, 0x002504, 0x00000001);
+ pms_unkn(pms, 0x06); /* unknown */
+ pms_unkn(pms, 0xb0); /* Disable bus access */
+ pms_op5f(pms, 0x00, 0x01);
+
+ pms_wr32(pms, 0x1002d4, 0x00000001);
+ pms_wr32(pms, 0x1002d0, 0x00000001);
+
+ pms_wr32(pms, 0x100210, 0x00000000);
+ pms_wr32(pms, 0x1002dc, 0x00000001);
+ pms_wr32(pms, state->pll.reg + 0, reg0_old);
+ pms_wr32(pms, state->pll.reg + 4, (state->N << 8) | state->M);
+
+ pms_wr32(pms, state->pll.reg + 0, reg0_new);
+ pms_wr32(pms, 0x1002dc, 0x00000000);
+ pms_wr32(pms, 0x100210, 0x80000000);
+ pms_unkn(pms, 0x07); /* unknown */
+
+ pms_unkn(pms, 0x0b);
+ pms_unkn(pms, 0xd0); /* Enable bus access again */
+ pms_op5f(pms, 0x00, 0x01);