To write data at the right offset, the kernel has to know some
parameters of this ring buffer, like the number of domains and the
maximum number of queries.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 3a99cc8..53817c0 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -441,6 +441,13 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)
BEGIN_NV04(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push, screen->sw->handle);
+ BEGIN_NV04(push, SUBC_SW(0x0190), 1);
+ PUSH_DATA (push, screen->query->handle);
+ // XXX: Maybe add a check for DRM version here ?
+ BEGIN_NV04(push, SUBC_SW(0x0600), 1);
+ PUSH_DATA (push, NV50_HW_PM_RING_BUFFER_MAX_QUERIES);
+ BEGIN_NV04(push, SUBC_SW(0x0604), 1);
+ PUSH_DATA (push, NV50_HW_PM_RING_BUFFER_NUM_DOMAINS);
BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
--
2.4.4
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