To Whom It May Concern,
Please allow me to introduce myself. My name is David Allen Blubaugh. I am currently in the developmental stages of a Field-Programmable-Gate-Array (FPGA) device for a high-performance computing application. I am currently evaluating the MyHDL environment for translating python source code to verilog. I am also wondering as to what would be necessary to interface both Scipy and Numpy to the MyHDL environment? I believe that there will definitely be the need for modifications done within Numpy framework in order to quickly prototype an algorithm, like the FFT, and have it translated to verilog. Do you have any additional suggestions? Thanks, David Blubaugh This e-mail transmission contains information that is confidential and may be privileged. It is intended only for the addressee(s) named above. If you receive this e-mail in error, please do not read, copy or disseminate it in any manner. If you are not the intended recipient, any disclosure, copying, distribution or use of the contents of this information is prohibited. Please reply to the message immediately by informing the sender that the message was misdirected. After replying, please erase it from your computer system. Your assistance in correcting this error is appreciated.
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