On 01.12.22 13:34:21, Dan Williams wrote: > In an RCH topology a CXL host-bridge as Root Complex Integrated Endpoint > the represents the memory expander. Unlike a VH topology there is no > CXL/PCIE Root Port that host the endpoint. The CXL subsystem maps this > as the CXL root object (ACPI0017 on ACPI based systems) targeting the > host-bridge as a dport, per usual, but then that dport directly hosts > the endpoint port. > > Mock up that configuration with a 4th host-bridge that has a 'cxl_rcd' > device instance as its immediate child. > > Reviewed-by: Alison Schofield <alison.schofi...@intel.com>
Reviewed-by: Robert Richter <rrich...@amd.com> > Signed-off-by: Dan Williams <dan.j.willi...@intel.com> > --- > tools/testing/cxl/test/cxl.c | 151 > +++++++++++++++++++++++++++++++++++++++--- > tools/testing/cxl/test/mem.c | 37 ++++++++++ > 2 files changed, 176 insertions(+), 12 deletions(-)
