Le 10/02/2023 à 13:43, Jonathan Cameron a écrit :
Hello Vishal Thanks a lot, things were failing because my kernel didn't have CONFIG_CXL_REGION_INVALIDATION_TEST=y. Now I am able to create a single ram region, either with a single device or multiple interleaved ones. However I can't get multiple separate ram regions. If I boot a config like yours below, I get 4 ram devices. How can I create one region for each? Once I create the first one, others fail saying something like below. I tried using other decoders but it didn't help (I still need to read more CXL docs about decoders, why new ones appear when creating a region, etc). cxl region: collect_memdevs: no active memdevs found: decoder: decoder0.0 filter: mem3Hi Brice, QEMU emulation currently only supports single HDM decoder at each level, so HB, Switch USP, EP (with exception of the CFMWS top level ones as shown in the example which has two of those). We should fix that... For now, you should be able to do it with multiple pxb-cxl instances with appropriate CFMWS entries for each one. Which is horrible but might work for you in the meantime.
Thanks Jonathan, this works fine: -object memory-backend-ram,id=vmem0,share=on,size=256M \ -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ -device cxl-type3,bus=root_port13,volatile-memdev=vmem0,id=cxl-vmem0 \ -object memory-backend-ram,id=vmem1,share=on,size=256M \ -device pxb-cxl,bus_nr=14,bus=pcie.0,id=cxl.2 \ -device cxl-rp,port=0,bus=cxl.2,id=root_port14,chassis=1,slot=2 \ -device cxl-type3,bus=root_port14,volatile-memdev=vmem1,id=cxl-vmem1 \ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.1.targets.0=cxl.2,cxl-fmw.1.size=4G
By the way, once configured in system ram, my CXL ram is merged into an existing "normal" NUMA node. How do I tell Qemu that a CXL region should be part of a new NUMA node? I assume that's what's going to happen on real hardware?We don't yet have kernel code to deal with assigning a new NUMA node. Was on the todo list in last sync call I think.
Good to known, thanks again. Brice
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