On Tue, Dec 02, 2025 at 02:15:47PM -0800, Alison Schofield wrote: > On Thu, Nov 20, 2025 at 05:20:17PM -0700, Dave Jiang wrote: > > Add a unit test that verifies the extended linear cache setup paths > > in the kernel driver. cxl_test provides a mock'd version. The test > > verifies the sysfs attribute that indicates extended linear cache support > > is correctly reported. It also verifies the sizing and offset of the > > regions and decoders. > > > > The expecation is that CFMWS covers the entire extended linear cache > > region. The first part is DRAM and second part is CXL memory in a 1:1 > > setup. The start base for hardware decoders should be offsetted by the > > DRAM size. > > Thanks! > > With this [ as: remove CONFIG_TRACE check ] > > Applied to pending: https://github.com/pmem/ndctl/commit/39085f7 Here is the corrected commit id: https://github.com/pmem/ndctl/commit/6834cd1
> > > >
