Adrian, Wow it's great to hear from you again!
adrian cockcroft wrote: >> Is it busier if there are four >> instructions active instead of one? > No, the IPC of a workload is a characteristic of that workload, all > the OS can do is give clock cycles to a workload What if you're using virtualization to consolidate two workloads? One is very tight highly optimized computational code with a CPI near one so it can only use one of 4 threads on Niagara; the other is database or app server code with a CPI of 4-6 so there are plenty of memory stall cycles to interleave other threads. When a thread of the first workload is scheduled on a core its capacity is filled with that single thread. When a thread of the second workload is scheduled it only consumes 25% of the capacity of the core. >> Is it any busier if it has both >> an integer and a floating point instruction active? > For shared FPU Niagara this is an issue, not an issue for most CPUs > By the time it could be addressed in software, will anyone still care > about Niagara? Probably not, but by then we'll probably care about some even more exotic architectures from all chip vendors. >> If some functional units may be dynamically >> reconfigured then is a core which owns such a unit and isn't using it >> any less busy than one which does not own such a unit? > No, but Intel hyperthreading and Power6 style reconfigurable pipelines > vary the work done per clock cycle independently of the application > workload, so not all clock ticks have the same value. Good point. Speaking of which, as the clock frequency changes with power management events, should the CPU utilization change along with it?
