On Friday 04 February 2005 12:01, Daniel Phillips wrote:
> It appears that it's impossible to do 16-bit integer adds or subtracts
> in 5ns on a Spartan 3.  Usually, when you are just pipelining
> everything, that's no big deal.  Just split the math into 8-bit
> stages.  (I've done it plenty of times.)  Unfortunately, there are two
> parts of the design, the vertical and horizontal rasterizers, that
> make it a bit challenging in that regard.

Hi Timothy,

I'm trying to understand what you mean by this.  I imagined that it doesn't 
matter how many stages it takes to step to the next horizontal pixel pair, 
because you're only concerned about throughput, not latency.  I must have 
missed something.

Regards,

Daniel
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